Display substrate and display device

ABSTRACT

A display substrate of the present disclosure includes a display region including sub-pixels, data lines, and gate lines; and a circuit region including a first sub-region and a second sub-region opposite to each other at two sides of the display region along a first direction. The first sub-region is provided with a plurality of multiplexing unit groups, each of which includes at least one multiplexing unit. The second sub-region is provided with a plurality of testing unit groups, each of which includes at least one testing unit. The circuit region is further provided with a plurality of driving unit groups, each of which includes at least one driving unit. The driving unit groups and the multiplexing unit groups are alternately arranged along an extending direction of the first sub-region in the first sub-region.

TECHNICAL FIELD

The present disclosure relates to the field of display technology, andin particular to a display substrate and a display device.

BACKGROUND

Organic Light Emitting Diode (OLED) display technology has been widelyapplied in the fields of a television, a smart phone, a wearable displaydevice, a Virtual Reality (VR) display, an automotive display, and thelike, due to advantages of lightness and thinness, flexibility,excellent shock resistance, fast response speed, and the like.

With the development of technology, a large “screen-to-body ratio (i.e.,a ratio of an area of an actual display region to a total area of thedisplay side)” has become one of appearance characteristics sought inthe display device. In particular, for a wearable display device, suchas a smart watch, an extremely narrow-bezel and even full-screen displayis becoming an important development trend for portability, visualeffect, and the like.

In the related art, some driving circuits for sub-pixels may be provideddirectly outside a display region of a display substrate. Obviously, theregion where the driving circuits are located cannot be directly used toperform a display, and thus corresponds to a “bezel” of a displaydevice.

SUMMARY

The present disclosure provides a display substrate and a displaydevice. In a first aspect, the present disclosure provides a displaysubstrate including a display region and a peripheral region, theperipheral region including a capacitor region, a circuit region, afan-out region and a joint region, wherein the display region isprovided with: a plurality of sub-pixels; a plurality of data linesextending along a first direction, each of the plurality of data linesbeing coupled to multiple sub-pixels; and a plurality of gate linesextending in a second direction intersecting the first direction, eachof the plurality of gate lines being coupled to multiple sub-pixels, thecircuit region is provided with a first sub-region and a secondsub-region which are opposite to each other at two sides of the displayregion along the first direction, respectively, the first sub-region isprovided with a plurality of multiplexing unit groups configured toprovide data signals to the plurality of data lines, and each of themultiplexing unit groups includes at least one multiplexing unit; thesecond sub-region is provided with a plurality of testing unit groupsconfigured to provide testing signals to the plurality of data lines,and each of the plurality of testing unit groups includes at least onetesting unit; the circuit region is further provided with a plurality ofdriving unit groups, each of the driving unit groups includes at leastone driving unit; the driving unit groups and the multiplexing unitgroups are alternately arranged in the first sub-region along anextending direction of the first sub-region, and the driving unit groupsand the testing unit groups are alternately arranged in the secondsub-region along an extending direction of the second sub-region; thecapacitor region is between the second sub-region and the displayregion, and is provided with a plurality of compensation capacitorunits, and each of the plurality of compensation capacitor units iscoupled to one of the plurality of data lines, the joint region is on aside of the first sub-region distal to the display region and includes aplurality of joints, at least some of the plurality of joints arecoupled to signal lines, the signal lines include multiplexing signallines coupled to multiplexing units, testing signal lines coupled totesting units and driving signal lines coupled to driving units; and thefan-out region is between the joint region and the first sub-region, andis provided with the multiplexing signal lines.

In some embodiments, the first sub-region includes a first arc region,the second sub-region includes a second arc region, and an edge of thefirst arc region proximal to the display region is closer to a center ofthe display region than an edge of the second arc region proximal to thedisplay region.

In some embodiments, the first arc region has a same circle center asthe second arc region, and a radius of the edge of the first arc regionproximal to the display region is smaller than a radius of the edge ofthe second arc region proximal to the display region by 210 μm˜420 μm.

In some embodiments, in the first sub-region, the multiplexing unitgroups include first multiplexing unit groups and second multiplexingunit groups, each of the first multiplexing unit groups includes Mmultiplexing units, each of the second multiplexing unit groups includesN multiplexing units, N and M are integers each greater than 1, and M<N,the second multiplexing unit groups are in the middle of the firstsub-region, the first multiplexing unit groups are at two ends of thefirst sub-region distal to the middle of the first sub-region; and/or

in the second sub-region, the testing unit groups include first testingunit groups and second testing unit groups, each of the first testingunit groups includes K testing units, each of the second testing unitgroups includes L testing units, L and K are integers each greater than1, and K<L, the second testing unit groups are in the middle of thesecond sub-region, and the first testing unit groups are at two ends ofthe second sub-region distal to the middle of the second sub-region.

In some embodiments, the circuit region is divided into a first halfregion and a second half region which are opposite to each other at twosides of the display region along the second direction;

the driving units include a plurality of gate driving units; and

the first half region is provided with multiple gate driving unitsconfigured to provide a gate driving signal to the plurality of gatelines.

In some embodiments, the display region is further provided with aplurality of control electrode lines extending along the seconddirection, and each of the plurality of control electrode line iscoupled to multiple sub-pixels;

the driving units further include a plurality of control electrodedriving units; and

the second half region is provided with a plurality of control electrodedriving units configured to provide a control electrode driving signalto the plurality of control electrode lines.

In some embodiments, the multiplexing signal lines include a pluralityof multiplexing control lines and a plurality of multiplexing datalines;

at least one of the multiplexing units includes a plurality ofmultiplexing transistors; a gate of each of the plurality ofmultiplexing transistors is coupled to one of the multiplexing controllines, a first electrode of each of the multiplexing transistors iscoupled to one of the data lines, and a second electrode of each of themultiplexing transistors is coupled to one of the multiplexing datalines; and

second electrodes of all multiplexing transistors in a same multiplexingunit are coupled to a same multiplexing data line, and second electrodesof the multiplexing transistors in different multiplexing units arecoupled to different multiplexing data lines.

In some embodiments, the testing signal lines include testing controllines and testing data lines;

at least one of the testing units includes a plurality of testingtransistors; a gate of each of the plurality of testing transistors iscoupled to one of the testing control lines, a first electrode of eachof the plurality of testing transistors is coupled to one of the datalines, and a second electrode of each of the plurality of testingtransistors is coupled to one of the testing data line; and

each of the testing data lines is coupled to multiple testing units.

In some embodiments, the testing signal lines are on a side of thecircuit region distal to the display region; and

the driving signal lines are on a side of the circuit region distal tothe display region.

In some embodiments, ends of the first sub-region closest to the secondsub-region are closer to the display region than ends of the secondsub-region closest to the first sub-region.

In some embodiments, the circuit region further includes:

connection sub-regions which are between and coupled to the ends of thefirst sub-region closest to the second sub-region and the ends of thesecond sub-region closest to the first sub-region.

In some embodiments, the display substrate further includes at least onepolysilicon resistor, wherein

each of the at least one polysilicon resistor is between and coupled totwo of the signal lines, the polysilicon resistor is on a side of theend of the first sub-region closest to the second sub-region, distal tothe display region, or the polysilicon resistor is on a side of theconnection sub-region distal to the display region.

In some embodiments, the testing signal lines are on a side of thecircuit region distal to the display region;

the driving signal lines are on a side of the circuit region distal tothe display region; and

the polysilicon resistor is on a side of the testing signal lines andthe driving signal lines distal to the display region.

In some embodiments, the display substrate further includes at least oneelectrostatic discharge unit, wherein

each of the at least one electrostatic discharge unit is coupled to oneof the signal lines and configured to release static charges in thesignal line to which it is coupled; the electrostatic discharge unit ison a side of the end of the first sub-region closest to the secondsub-region, distal to the display region, or the electrostatic dischargeunit is on a side of the connection sub-region distal to the displayregion.

In some embodiments, the testing signal lines are on a side of thecircuit region distal to the display region;

the driving signal lines are on a side of the circuit region distal tothe display region; and

the electrostatic discharge units are on a side of the testing signallines and the driving signal lines distal to the display region.

In some embodiments, the multiplexing signal lines include a pluralityof multiplexing control lines and a plurality of multiplexing datalines; and the signal lines coupled to each of electrostatic dischargeunits are the testing signal lines or the multiplexing control lines.

In some embodiments, the driving signal lines include a high level lineand a low level line, the high level line is coupled to a high levelsignal source, and the low level line is coupled to a low level signalsource; and

each of the electrostatic discharge units includes a first dischargetransistor and a second discharge transistor; a gate and a firstelectrode of the first discharge transistor are coupled to the highlevel line, and a second electrode of the first discharge transistor iscoupled to the signal line corresponding to the electrostatic dischargeunit; and a gate and a first electrode of the second dischargetransistor are coupled to the signal line corresponding to theelectrostatic discharge unit, and a second electrode of the seconddischarge transistor is coupled to the low level line.

In some embodiments, at least some of different data lines are coupledto different numbers of sub-pixels; and

except for the data line coupled to a largest number of sub-pixels, eachof the remaining data lines is coupled to one of the compensationcapacitor units.

In some embodiments, each of the compensation capacitor units includesone or more compensation capacitors;

except for the data line coupled to the largest number of sub-pixels,the number n of the compensation capacitors in the compensationcapacitor unit coupled to each of the remaining data lines, satisfies:

N=Nmax−N;

wherein Nmax is the number of the sub-pixels coupled to the data linecoupled to the largest number of the sub-pixels, and N is the number ofthe sub-pixels coupled to the data line coupled to the compensationcapacitor unit.

In some embodiments, the data line is coupled to first electrodes of allthe compensation capacitors in the compensation capacitor unit coupledto the data line; and

second electrodes of all the compensation capacitors in the compensationcapacitor unit are coupled to a same constant level signal line.

In some embodiments, multiple sub-pixels coupled to each of the datalines are arranged in a column along the first direction; and

the compensation capacitor unit coupled to each of the data lines isbetween a column of sub-pixels coupled to the data line and the secondsub-region along the first direction.

In some embodiments, the display substrate is an organic light emittingdiode display substrate.

The present disclosure further provides a display device, including thedisplay substrate in any one of the above mentioned embodiments.

In some embodiments, the display device is a wearable display device.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings are intended to provide a further understanding of theembodiments of the present disclosure, and constitute a part of thespecification. The drawings together with the embodiments of the presentdisclosure are used for explaining the present disclosure, but notintended to limit the present disclosure. The above and other featuresand advantages will become more apparent to those skilled in the art bydescribing in detail exemplary embodiments thereof with reference to thedrawings, in which:

FIG. 1 is a schematic diagram illustrating a structure of a displaysubstrate according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram illustrating a structure of a displaysubstrate (some lines not shown) according to an embodiment of thepresent disclosure;

FIG. 3 is a schematic diagram illustrating a pixel circuit in a displaysubstrate according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram illustrating a structure of a displaysubstrate according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating a structure of a displaysubstrate (some lines not shown) according to an embodiment of thepresent disclosure;

FIG. 6 is a schematic diagram illustrating a circuit of a multiplexingunit in a display substrate according to an embodiment of the presentdisclosure;

FIG. 7 is a schematic diagram illustrating a circuit of a testing unitin a display substrate according to an embodiment of the presentdisclosure;

FIG. 8 is a schematic diagram illustrating a circuit of a testing unitin a display substrate according to an embodiment of the presentdisclosure;

FIG. 9 is a circuit diagram of a gate shift register in a displaysubstrate according to an embodiment of the present disclosure;

FIG. 10 is a timing diagram for driving a gate shift register in adisplay substrate according to an embodiment of the present disclosure;

FIG. 11 is a circuit diagram of a control electrode shift register in adisplay substrate according to an embodiment of the present disclosure;

FIG. 12 is a timing diagram for driving a control electrode shiftregister in a display substrate according to an embodiment of thepresent disclosure;

FIG. 13 is a schematic diagram illustrating a partial structure at aconnection sub-region of a display substrate according to an embodimentof the present disclosure;

FIG. 14 is a schematic diagram illustrating distribution densities ofdifferent units in a display substrate according to an embodiment of thepresent disclosure;

FIG. 15 is a schematic diagram illustrating distribution densities ofdifferent units in a display substrate according to an embodiment of thepresent disclosure;

FIG. 16 is a schematic diagram illustrating a circuit of anelectrostatic discharge unit in a display substrate according to anembodiment of the present disclosure; and

FIG. 17 is a schematic diagram illustrating a partial structure of acompensation capacitor unit of a display substrate according to anembodiment of the present disclosure.

In the drawings of the embodiments of the present disclosure, thereference numerals are as below:

-   -   1: sub-pixel; 11: data line; 12: gate line; 13: control        electrode line; 19: anode signal line;    -   2: multiplexing unit; 21: multiplexing transistor;    -   3: testing unit; 31: testing transistor; 311: first testing        transistor; 312: second testing transistor; 313: third testing        transistor; 314: fourth testing transistor; 315: fifth testing        transistor;    -   4: driving unit; 41: gate driving unit; 42: control electrode        driving unit;    -   5: compensation capacitor unit; 51: compensation capacitor;    -   6: joint; 62: multiplexing signal line; 621: multiplexing        control line; 622: multiplexing data line; 63: testing signal        line; 631: testing control line; 6311: first testing control        line; 6312: second testing control line; 6313: third testing        control line; 632: testing data line; 6321: first testing data        line; 6322: second testing data line; 6323: third testing data        line;    -   64: driving signal line; 641: high level line; 642: low level        line;    -   71: polysilicon resistor; 711: first polysilicon resistor; 712:        second polysilicon resistor; 72: electrostatic discharge unit;        721: first discharge transistor; 722: second discharge        transistor;    -   91: display region; 92: circuit region; 921: first sub-region;        922: second sub-region; 923: connection sub-region; 93: fan-out        region; 94: joint region; 95: capacitor region; 991: first        direction; 992: second direction;    -   T1: first transistor; T2: second transistor; T3: third        transistor; T4: fourth transistor; T5: fifth transistor; T6:        sixth transistor; T7: seventh transistor; Cst: storage        capacitor; Reset: first reset terminal; Reset′: second reset        terminal; Vinit: initializing terminal; Gate: gate line        terminal; Data: data line terminal; EM: control electrode line        terminal; VDD: anode signal terminal; VSS: cathode signal        terminal;    -   K1: first gate transistor; K2: second gate transistor; K3: third        gate transistor; K4: fourth gate transistor; K5: fifth gate        transistor; K6: sixth gate transistor; K7: seventh gate        transistor; K8: eighth gate transistor; C1: first gate        capacitor; C2: second gate capacitor; N1: first gate node; N2:        second gate node; N3: third gate node;    -   M1: first control electrode transistor; M2: second control        electrode transistor; M3: third control electrode transistor;        M4: fourth control electrode transistor; M5: fifth control        electrode transistor; M6: sixth control electrode transistor;        M7: seventh control electrode transistor; M8: eighth control        electrode transistor; M9: ninth control electrode transistor;        M10: tenth control electrode transistor; C1′: first control        electrode capacitor; C2′: second control electrode capacitor;        C3′: third control electrode capacitor; N1′: first control        electrode node; N2′: second control electrode node; N3′: third        control electrode node; N4′: fourth control electrode node.

DETAILED DESCRIPTION

In order to make those skilled in the art better understand thetechnical solutions of the embodiments of the present disclosure, adisplay substrate and a display device in the embodiments of the presentdisclosure will be described in detail below with reference to theaccompanying drawings.

The embodiments of the present disclosure will be described more fullyhereinafter with reference to the accompanying drawings, but theembodiments shown may be embodied in different forms and should not beconstrued as limited to the embodiments set forth herein. On thecontrary, the purpose of providing these embodiments is to make thepresent disclosure thorough and complete, and to enable those skilled inthe art to fully understand the scope of the present disclosure.

The embodiments of the present disclosure may be described withreference to plan and/or cross-sectional views by way of idealizedschematic illustrations of the present disclosure. Accordingly, theexample drawings may be modified in accordance with manufacturingtechniques and/or tolerances.

The embodiments of the present disclosure and features of theembodiments may be combined with each other without conflict.

The terminology used in the present disclosure is for the purpose ofdescribing particular embodiments only and is not intended to limit thepresent disclosure. As used in the present disclosure, the term “and/or”includes any and all combinations of one or more of the associatedlisted items. As used in the present disclosure, the singular forms “a(an)” and “the” are intended to include the plural forms as well, unlessthe context clearly indicates otherwise. As used in the presentdisclosure, the terms “comprising (including)”, “consisting of”, specifythe presence of features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used in the present disclosure have the same meaning as commonlyunderstood by those skilled in the art. It will be further understoodthat the terms, such as those defined in commonly used dictionaries,should be interpreted as having meanings that are consistent with theirmeanings in the context of the related art and the present disclosure,and will not be interpreted in an idealized or overly formal senseunless expressly so defined herein.

The embodiments of the present disclosure are not limited to theembodiments shown in the drawings, but include modifications ofconfigurations formed based on manufacturing processes. Thus, theregions illustrated in the drawings have schematic properties, and theshapes of the regions shown in the drawings illustrate specific shapesof regions of elements, but are not intended to be restrictive.

In the embodiments of the present disclosure, in the drawings, a size ofa component, a thickness of a layer, or a region may be exaggerated forclarity. Therefore, one implementation of the present disclosure is notnecessarily limited to the size, and the shape and size of the componentin the drawings do not reflect a true scale. Further, the drawingsschematically show ideal examples, and one implementation of the presentdisclosure is not limited to the shape, the numerical value, and thelike shown in the drawings.

In the embodiments of the present disclosure, ordinal numbers such as“first”, “second”, “third”, and the like are provided to avoid confusionof constituent elements, and are not limited in number.

In the embodiments of the present disclosure, for convenience, the wordsand phrases indicating orientations or positional relationships, such as“middle”, “upper”, “lower”, “front”, “rear”, “vertical”, “horizontal”,“top”, “bottom”, “inner”, “outer”, and the like are used to explainpositional relationships of constituent elements with reference to thedrawings, only for convenience of description and simplification ofdescription, but not to indicate or imply that the device or elementreferred to must have a specific orientation, be configured and operatedin a specific orientation, and thus, should not be construed as limitingthe present disclosure. The positional relationship of the componentelements is changed as appropriate in accordance with the direction inwhich the component elements are described. Therefore, the words andphrases described in the specification are not limited thereto, and maybe replaced as appropriate depending on the cases.

In the embodiments of the present disclosure, the terms “mounted”,connected”, and “coupled” are to be construed broadly unless otherwiseexplicitly specified or limited. For example, it may be a fixedconnection, or a detachable connection, or an integral connection; itmay be a mechanical connection, or an electrical connection; and it maybe either directly or indirectly through intervening components, or twoelements may be interconnected. The specific meaning of the above termsin the present disclosure may be understood in a specific case to thoseskilled in the art.

In the embodiment of the present disclosure, a transistor refers to anelement including at least three terminals of a gate, a drain, and asource. The transistor has a channel region between the drain (a drainterminal, a drain region, or a drain electrode) and the source (a sourceterminal, a source region, or a source electrode), and a current mayflow through the drain, the channel region, and the source. It should benoted that, in the present disclosure, the channel region refers to aregion through which the current mainly flows.

In the embodiments of the present disclosure, a first electrode may be adrain, and a second electrode may be a source, or a first electrode maybe a source and a second electrode may be a drain. In the case of usingtransistors of opposite polarities, or in the case where the directionof current during circuit operation changes, the functions of the“source” and the “drain” may be interchanged. Therefore, in the presentdisclosure, the “source” and the “drain” may be interchanged with eachother.

In the embodiments of the present disclosure, “electrically coupled”includes a case where constituent elements are coupled together by anelement having some kind of electrical action. The “element having somekind of electrical action” is not particularly limited as long as it cantransmit and receive an electrical signal between connected components.Examples of the “element having some kind of electric action” includenot only an electrode and a wiring but also a switching element such asa transistor, a resistor, an inductor, a capacitor, other elementshaving various functions, and the like.

In the embodiment of the present disclosure, “parallel” means a state inwhich an angle formed by two straight lines is more than −10° and lessthan 10°, and therefore, includes a state in which the angle is morethan −5° and less than 5°. In addition, “perpendicular” means a state inwhich an angle formed by two straight lines is more than 80° and lessthan 100°, and therefore includes a state in which an angle is more than8° and less than 95°.

In the embodiments of the present disclosure, “film” and “layer” may beinterchanged with one another. For example, a “conductive layer” may besometimes replaced with a “conductive film”. Similarly, an “insulatingfilm” may be replaced with an “insulating layer”.

In the embodiments of the present disclosure, “about” refers to a valuewithin the allowable process and measurement error range without strictlimits

In a first aspect, referring to FIGS. 1 to 17, a display substrate isprovided according to an embodiment of the present disclosure.

The display substrate according to an embodiment of the presentdisclosure is a substrate, such as an array substrate provided with aThin Film Transistor (TFT) array, in a display device.

The display substrate according to an embodiment of the presentdisclosure includes a display region 91 and a peripheral region, whichsurrounds the display region 91 and includes a capacitor region 95, acircuit region 92, a fan-out region 93, and a joint region 94.

The display region 91 is provided with: a plurality of sub-pixels 1; aplurality of data lines 11 extending in a first direction 991, each ofthe plurality of data lines 11 being coupled to multiple sub-pixels 1; aplurality of gate lines 12 extending in a second direction 992intersecting the first direction 991, each of the plurality of gatelines 12 being coupled to multiple sub-pixels 1.

The circuit region 92 surrounds the display region 91, and includes afirst sub-region 921 and a second sub-region 922 opposite to each otherrespectively on two sides of the display region 91 in the firstdirection 991. The first sub-region 921 is provided with a plurality ofmultiplexing unit groups configured to provide data signals to theplurality of data lines 11. Each of the multiplexing unit groupsincludes at least one multiplexing unit 2. The second sub-region 922 isprovided with a plurality of testing unit groups configured to providetest signals to the plurality of data lines 11. Each of the testing unitgroups includes at least one testing unit 3. The circuit region 92 isfurther provided with a plurality of driving unit groups, and each ofthe driving unit groups includes at least one driving unit 4. In thefirst sub-region 921, the driving unit groups and the multiplexing unitgroups are alternately arranged along a circumferential direction of thedisplay region 91, and in the second sub-region 922, the driving unitgroups and the testing unit groups are alternately arranged along thecircumferential direction.

The capacitor region 95 is between the second sub-region 922 and thedisplay region 91. A plurality of compensation capacitor units 5 isprovided in the capacitor region 95, and each of the plurality ofcompensation capacitor units 5 is coupled to one of the data lines 11.

The joint region 94 is on a side of the first sub-region 921 distal tothe display region 91. A plurality of joints 6 are provided in the jointregion 94, and at least some of the joints 6 are coupled to signallines. The signal lines include multiplexing signal lines 62 coupled tomultiplexing units 2, testing signal lines 63 coupled to testing units3, and driving signal lines 64 coupled to driving units 4.

The fan-out region 93 is between the joint region 94 and the firstsub-region 921. A plurality of multiplexing signal lines 62 are providedin the fan-out region 93.

Referring to FIGS. 1, 2, 4 and 5, the display substrate according to anembodiment of the present disclosure is divided into a plurality ofregions, among which the region in the center is the display region 91(i.e., an AA region) for displaying. The sub-pixels 1 for displaying areprovided in the display region 91.

A sub-pixel 1 is the smallest structure that may be used toindependently display a desired content, i.e., the sub-pixel 1 is thesmallest “point” that may be independently controlled in the displaydevice.

The sub-pixel 1 may have any type of form as long as an independentdisplay may be achieved.

Exemplarily, the sub-pixel 1 may include a pixel circuit to emit lightin a desired brightness under a control of a corresponding gate line 12,a corresponding data line 11, and the like. For example, referring toFIG. 3, the pixel circuit may have a structure of 7T1C (i.e., including7 transistors and 1 capacitor) including a first transistor T1, a secondtransistor T2, a third transistor T3, a fourth transistor T4, a fifthtransistor T5, a sixth transistor T6, a seventh transistor T7, a storagecapacitor Cst, an organic light emitting diode OLED, a first resetterminal Reset, a second reset terminal Reset′, an initializing terminalVinit, a gate line terminal Gate, a data line terminal Data, a controlelectrode terminal EM, an anode signal terminal VDD, a cathode signalterminal VSS, and the like. Each of the transistors may be a P-typetransistor (e.g., PMOS). The data line terminal Data may be coupled tothe data line 11, the gate line terminal Gate may be coupled to the gateline 12, the control electrode line terminal EM may be coupled to acontrol electrode line 13, both the first reset terminal Reset and thesecond reset terminal Reset′ may be coupled to the gate line in aprevious row, the second reset terminal Reset′ may also be coupled tothe gate line in the current row, and the other terminals may also becoupled to corresponding signal sources.

That is, in each of the sub-pixels 1 of the display substrate accordingto an embodiment of the present disclosure, an organic light emittingdiode OLED may be used as a light emitting element, i.e., specifically,the display substrate may be an organic light emitting diode displaysubstrate, or the display substrate may be an array substrate providedwith a thin film transistor (TFT) array.

Different sub-pixels 1 may emit light of different colors, so that acolor display may be achieved by mixing light from different sub-pixels1. When the color display is to be implemented, multiple sub-pixels 1 ofdifferent colors arranged together may form a “pixel (i.e., pixelunit)”, that is, light emitted by these sub-pixels 1 is mixed togetherto form a “point” visually. For example, one pixel may be constituted ofthree sub-pixels 1 which emit light of three colors of red, green, andblue respectively. Alternatively, a color display may be achieved by“sharing” a sub-pixel between adjacent sub-pixels 1 without a definitepixel (or pixel unit).

Referring to FIGS. 1, 2, 4 and 5, the display region 91 is furtherprovided with data lines 11 extending in a first direction 991, and gatelines 12 extending in a second direction 992. The first direction 991crosses (i.e., is not parallel to) the second direction 992, so that onesub-pixel 1 may be defined at one of crossing positions where the datalines 11 crosses the gate lines 12. The sub-pixel 11 at the crossingposition may be for display by a common control of the gate line 12 andthe data line 11.

In some embodiments, the first direction 991 is perpendicular to thesecond direction 992, i.e., the first direction 991 may be a columndirection (a vertical direction in FIGS. 1, 2, 4 and 5), and the seconddirection 992 may be a row direction (a lateral direction in FIGS. 1, 2,4 and 5) perpendicular to the column direction.

It is to be understood that, the first direction 991 and the seconddirection 992 are substantially only two directions with respect to eachother respectively corresponding to the data lines 11 and the gate lines12. The two directions are not necessarily a column direction and a rowdirection, and have no necessary relationship with a shape, a position,a placement, and the like, of the display substrate (or the displaydevice).

In some embodiments, the sub-pixels 1 in the display region 91 may bearranged in an array, i.e., the sub-pixels 1 may be arranged in multiplerows and multiple columns. Each row of sub-pixels 1 is coupled to onegate line 12, and each column of sub-pixels 1 is coupled to one dataline 11.

It is to be understood that, the sub-pixels 1 are not necessarilyarranged in an array, and each of the data and gate lines 11 and 12 isnot necessarily coupled to the sub-pixels 1 in a same column and rowrespectively.

Referring to FIGS. 1, 2, 4 and 5, the region outside the display region91 is the circuit region 92 surrounding the display region 9, so thatthe display region 91 as a whole has a shape of an annulus. A peripheralregion of the display region 91 is not used for displaying, so that itcorresponds to a “bezel” of the display device.

The peripheral region includes the circuit region 92 surrounding thedisplay region 91, so that the circuit region 92 as a whole also has ashape of an annulus and includes a first sub-region 921 and a secondsub-region 922 opposite to each other on two sides of the display region91 in the first direction 991. The first sub-region 921 and the secondsub-region 922 correspond to for example a “lower half region” and an“upper half region” in FIGS. 1 and 2 respectively. The first sub-region921 is provided with a plurality of multiplexing units 2 (MUX), whichare coupled to the data lines 11 at one side (a lower side in FIGS. 1,2, 4 and 5) for providing data signals (data voltages) to the data lines11 during displaying. The second sub-region 922 is provided with aplurality of testing units 3 (CT), which are coupled to the data lines11 at the other side (a upper side in FIGS. 1, 2, 4 and 5) for providingtesting signals to the data lines 11 during testing to detect whetherthe display substrate is defective.

In addition, the circuit region 92 is provided with a plurality ofdriving units 4 for providing other driving signals.

In some embodiments, at least some of the driving units 4 are configuredto provide driving signals to the gate lines 12, i.e., at least some ofthe driving units 4 are coupled to the above gate lines 12 and are usedto provide signals to the gate lines 12 for controlling the working ofthe sub-pixels 1 coupled to respective gate lines 12.

It can be seen that the above multiplexing units 2 constitute theplurality of “multiplexing unit groups”, each of which includes onemultiplexing unit 2 or multiple multiplexing units 2 consecutivelyarranged. The testing units 3 constitute the plurality of “testing unitgroups”, each of which includes one testing unit 3 or multiple testingunits 3 consecutively arranged. The driving units 4 constitute theplurality of “driving unit groups”, each of which includes one drivingunit 4 or multiple driving units 4 consecutively arranged. Thus, thecircuit region 92 is provided with different units which are “mixed” inarrangement.

Specifically, referring to FIGS. 1, 2, 4, 5, 14 and 15, in the firstsub-region 921, the driving unit groups and the multiplexing unit groupsare alternately arranged in the “peripheral direction”.

The term “peripheral direction” refers to a direction of rotation abouta center of a planar pattern, or a direction of clockwise orcounterclockwise rotation about an edge of a planar pattern.

That is, in the embodiment of the present disclosure, when traversingthe circuit region 92 substantially having a shape of an annulus in aclockwise or a counterclockwise direction, the driving unit groups andthe multiplexing unit groups are alternately arranged in the firstsub-region 921, that is, in a manner of one driving unit group-onemultiplexing unit group-one driving unit group-one multiplexing unitgroup . . . and so on. Of course, each “group” includes one or moreconsecutive corresponding units, so that the driving units 4 and themultiplexing units 2 in the first sub-region 921 are “mixed” inarrangement (but multiple same units may be consecutively arranged),rather than being concentrated in different positions in the firstsub-regions 921, respectively.

Specifically, in FIGS. 1, 2, 4, 5, 14 and 15, in the second sub-region922, the driving unit groups and the testing unit groups are alternatelyarranged in the peripheral direction.

That is, when traversing the circuit region 92 substantially having ashape of an annulus in a clockwise or a counterclockwise direction, thedriving unit groups and the testing unit groups are alternately arrangedin the second sub-region 922, that is, in a manner of one driving unitgroup-one testing unit group-one driving unit group-one testing unitgroup . . . and so on. Of course, each “group” includes one or moreconsecutive corresponding units, so that the driving units 4 and thetesting units 2 in the second sub-region 922 are “mixed” in arrangement(but multiple same units may be consecutively arranged), rather thanbeing concentrated in different positions in the second sub-regions 922,respectively.

In an exemplary embodiment, in the first sub-region 921, a number of themultiplexer units 2 between adjacent two driving units 4 is determinedaccording to a size of a gap between the adjacent two driving units 4.

In an exemplary embodiment, in the second sub-region 922, a number oftesting units 3 between two adjacent driving units 4 is determinedaccording to a size of a gap between the two adjacent driving units 4.

In an exemplary embodiment, a gap between any two adjacent units (e.g.,the multiplexer units 2, the testing units 3 and the driving units 4) islarger than 1 micrometer. Exemplarily, a gap between two adjacentdriving units 4 may be 1.5 micrometers, a gap between the driving unit 4and adjacent multiplexing unit 2 may be 1.5 micrometers, and a gapbetween the driving unit 4 and adjacent testing unit 3 may be 1.5micrometers, and the like.

The above “gap” refers to a shortest straight line distance betweenelements in two adjacent units, respectively.

Obviously, circuits in the circuit region 92 also need certain signalsto operate, so that the peripheral region is further provided with ajoint region 94 for introducing these signals. The joint region 94 isprovided with a plurality of joints 6 coupled to signal lines. Thesignal lines may include multiplexing signal lines 62, testing signallines 63, driving signal lines 64, etc., for respectively supplyingpower to the multiplexing units 2, the testing units 3, and the drivingunits 4. Of course, the signal lines are coupled to corresponding unitsand joints 6 respectively.

The joints 6 (Pads or Pins) refers to a structure in the displaysubstrate that may acquire signals and introduce the signals to thesignal lines.

Specifically, the joints 6 may be used for bonding with a flexibleprinted circuit (FPC) or a driving chip, so as to obtain the signalsfrom the flexible printed circuit or the driving chip.

Optionally, the joints 6 may be used to be in contact with testingprobes of a testing device to obtain signals from the testing probes.

Referring to FIGS. 1, 2, 4 and 5, the joint region 94 is on a side(i.e., an outer side) of the circuit region 92 distal to the displayregion 91, and the fan-out region 93 is further provided between thejoint region 94 and the first sub-region 921. The fan-out region (Fanoutregion) 93 is provided with a plurality of multiplexing signal lines 62,that is, after being led out from the joint region 94, the multiplexingsignal lines 62 are coupled to corresponding multiplexing units 2 acrossthe fan-out region 93.

Generally, the number of multiplexing signal lines 62 is much more thana sum of the numbers of testing signal lines 63 and the driving signallines 64. Therefore, by providing the fan-out region 93 between thejoint region 94 and the first sub-region 921 provided with themultiplexing units 2, the much more number of multiplexing signal lines62 may be coupled to the multiplexing units 2 with a less distance.Although the driving signal lines 64 and the testing signal lines 63need to extend a long distance to be coupled to the driving units 4 andthe testing units 3 respectively, due to the less number of the drivingsignal lines 64 and the testing signal lines 63, a total length of allthe driving signal lines 64 and the testing signal lines 63 is not toolarge. Therefore, by the above design, the total length and the occupiedlayout region of the signal lines may be reduced, the bezel of thedisplay device may be reduced, and the screen-to-body ratio isincreased.

Of course, in addition to the multiplexing signal lines 62, a part ofthe driving signal lines 64 and the test signal lines 63 may be in thefan-out region 93.

Referring to FIGS. 1 and 2, since there is no fan-out region 93 at aside (the upper side in FIGS. 1 and 2) where the second sub-region 922is located, there may be a space for other structures. Therefore, acapacitor region 95 may be provided between the second sub-region 922and the display region 91. A plurality of compensation capacitor units 5coupled to the data lines 11 are provided in the capacitor region 95 forcompensating capacitance differences between different data lines 11,which will be described in detail later.

Referring to FIGS. 1, 2, 4 and 5, the units (including the multiplexingunits 2, the testing units 3, and the driving units 4) in the displaysubstrate according to an embodiment of the present disclosure arearranged to be mixed, so that the units may provide signals to thecorresponding data lines 11, the corresponding gate lines 12, and thelike, respectively, in a less distance. Meanwhile, by a relativelyuniform distribution of the structures on the display substrate, thespace of the display substrate may be fully utilized, the bezel of thedisplay device may be reduced, and the screen-to-body ratio may beincreased.

In some embodiments, the first sub-region 921 includes a first arcregion and the second sub-region 922 includes a second arc region. Anedge of the first arc region 921 proximal to the display region 91 iscloser to a center of the display region 92 than an edge of the secondarc region proximal to the display region 92.

Referring to FIGS. 1, 2 and 14, the first sub-region 921 and the secondsub-region 922 may include a part of an arc (or an annulus).

Exemplarily, a main surface of the display substrate may have a shape ofa substantial circle, and the display region 91 may also have a shape ofa circle, so that the circuit region 92 may substantially have a shapeof an annulus surrounding and outside the circular display region 91.Each of the first sub-region 921 and the second sub-region 922 has ashape of a “half annulus” (an “upper half annulus” and a “lower halfannulus” in FIGS. 1 and 2) with openings of the two opposite to eachother.

Moreover, the edge of the first arc region (the first sub-region 921)proximal to the display region 91 is closer to the center of the displayregion 91 than the edge of the second arc region (the second sub-region922) proximal to the display region 91, or the first arc region has aninner edge “shorter” than that of the second arc region because thecapacitor region 95 is further provided proximal to the inner edge ofthe second sub-region 922.

In some embodiments, the first arc region (the first sub-region 921) hasa same center of a circle as the second arc region (the secondsub-region 922), and a radius of the edge of the first arc regionproximal to the display region 91 is smaller by 210˜420 μm than a radiusof the edge of the second arc region proximal to the display region 91.

Exemplarily, the above first arc region and the second arc region may beconcentric, with an inner diameter difference therebetween in a range of210 μm˜420 μm (the first arc region has a smaller inner diameter),further in a range of 250 μm 350 μm.

The main surface of the display substrate may be a side surface of thebase substrate thereof, that is, a surface of the base substrate of thedisplay substrate according to an embodiment of the present disclosuremay have a shape of a circle.

The base substrate is a base for supporting other structures of thedisplay substrate. The base substrate is of a substantial sheet made ofa material such as glass, silicon (e.g., monocrystalline silicon), apolymer material (e.g., polyimide), may be rigid or flexible, and has athickness of millimeter order.

In the embodiment of the present disclosure, “A is substantially B”refers to that, on a scale of A as a whole, A conforms to features of B,but on a scale that is significantly smaller than A as a whole, A maynot completely conform to features of B. For example, “A issubstantially circular” refers to that A may be a perfect circle orellipse, or A as a whole may be a circle or ellipse with some detailedparts being not strictly circular. For example, a small part of theboundary of A may be a straight line, a broken line, and the like. Foranother example, a small part of the boundary of A may be an arc whichis an approximate arc but not a strict arc. For another example, partsof the boundary of A at different positions may be arcs with differentdiameters.

Referring to FIGS. 1 and 2, when the circuit region 92 is an “annulus”,most of the circuit region 92 is provided with corresponding data lines11 and gate lines 12 (i.e., there are corresponding sub-pixels 1 in boththe row and column directions). In this case, the multiplexing units 2,the testing units 3, and the driving units 4 in the circuit region 92are arranged to be mixed, which is most beneficial for the units to becoupled to corresponding data lines 11 and gate lines 12 with a lessdistance.

Of course, a specific shape of the display substrate and the regionsthereof are not limited to the above shapes, and the display substrateand the regions thereof may have other shapes.

For example, in other embodiments, the first sub-region 921 includes afirst U-shaped region, and the second sub-region 922 includes a secondU-shaped region.

Referring to FIGS. 4, 5 and 15, as another implementation according toan embodiment of the present disclosure, a main surface of the displaysubstrate may also have a shape of substantially an arc angle rectangle(referred to as a rectangle with arc corners, a rounded rectangle or anarcuate rectangle), and the display region 91 may also have a shape ofsubstantially an arc angle rectangle, so that the circuit region 92 issubstantially an arcuate rectangular ring surrounding the arcrectangular display region 91.

Thus, each of the first sub-region 921 and the second sub-region 922 isa “U-shaped ring” (an “upper U-shaped ring” and a “lower U-shaped ring”with two openings opposite to each other in FIGS. 4 and 5), and a bottomof each of the upper U-shaped ring and the lower U-shaped ring is of twostraight lines other than arcs.

The “arc angle rectangle” refers to a shape similar to a rectangle,which has four straight sides with four “arc corners” of relativelyuniform transition other than four right angles. The four “arc angles”may further be referred to as “round angles”, that is, the “arc anglerectangle” may also be a “rounded rectangle”.

Accordingly, the circuit region 92 is “an annulus region of an arc anglerectangle”, which is an annular region sandwiched between two “arc anglerectangles” of different sizes, and thus may also be considered as a“hollowed-out arc angle rectangle”. Of course, further, the circuitregion 92 may also be “an annulus region of a rounded rectangle” (i.e.,a “hollowed-out rounded rectangle”).

In some embodiments, the first U-shaped ring has a width (i.e., adistance between two straight lines) approximately equal to that of thesecond U-shaped ring, and the first U-shaped ring (i.e., a distance froma bottom of the U-shape ring distal to its opening to its opening) has aheight approximately equal to that of the second U-shaped ring.

Referring to FIGS. 4 and 5, the first U-shaped ring may have asubstantially same size as the second U-shaped ring, so that the firstU-shaped ring and the second U-shaped ring may be substantially“symmetrical up and down” (i.e., symmetrical along the direction 992).

In some embodiments, an inner edge of the first U-shaped ring (i.e., anouter edge of the display region 91) includes two first arc boundaries,and an inner edge of the second U-shaped region (i.e., the outer edge ofthe display region 91) includes two second arc boundaries. An inner edgeof the circuit region (i.e., the outer edge of the display region 91)further includes: two first straight boundaries extending in the firstdirection 991 (each of the first straight boundaries is across the firstsub-region 921 and the second sub-region 922), a second straightboundary (belonging to the first sub-region 921) and a third straightboundary (belonging to the second sub-region 922) extending in thesecond direction 992.

It should be understood that, of course, outer edges of the firstsub-region 921 and the second sub-region 922 (i.e., an outer edge of thecircuit region 92) should have a shape substantially similar to theirinner edges.

Further, distances from any point of the inner edge of the circuitregion 92 to the outer edge thereof along a normal direction are thesame, i.e., the circuit region 92 may have a same width at any point ofthe inner edge to the outer edge of the circuit region 92.

In some embodiments, in the first sub-region 921 and the secondsub-region 922, multiple driving units 4 are arranged along the firststraight boundaries. In the first sub-section 921, multiple multiplexingunits 2 are arranged along the second straight boundary. In the secondsub-section 922, multiple testing units 3 are arranged along the thirdstraight boundary.

In some embodiments, in the first sub-section 921, the driving units 4and the multiplexing units 2 are alternately arranged along the firstarc boundary; and in the second sub-section 922, the driving units 4 andthe testing units 3 are alternately arranged along the second arcboundary.

That is, referring to FIGS. 4 and 5, when the first sub-region 921 andthe second sub-region 922 include the above “annular region of an arcangle rectangle”, different units may be arranged in a mixed manner onlyat positions along “arc angles of the annular region of the arc anglerectangle”, and only a same type of units may be arranged at positionsalong “edges of a straight line of the annular region of the arc anglerectangle”.

In some embodiments, in the first sub-region 921, a trace of connectingcenter points of coverage regions of the driving units 4 arranged alongthe first arc boundary constitute a first arc trace, a trace ofconnecting center points of coverage regions of the multiplexing units 2arranged along the first arc boundary constitute a second arc trace.Circle centers of the first and second arc traces coincide with a circlecenter of the first arc boundary.

In some embodiments, in the second sub-region 922, a trace of connectingcenter points of coverage regions of the driving units 4 arranged alongthe second arc boundary constitute a third arc trace, a trace ofconnecting center points of coverage regions of the testing units 3arranged along the second arc boundary constitute a fourth arc trace.Circle centers of the third and fourth arc traces coincide with a circlecenter of the second arc boundary.

That is, referring to FIGS. 4 and 5, in each of the sub-regions, eachtype of the units along corresponding arc boundary are arranged along anarc trace. Circles corresponding to the arc traces of two types of unitsalong a same arc boundary, and a circle corresponding to the same arcboundary, are concentric.

In some embodiments, in first sub-region 921, the multiplexing unitgroups includes first multiplexing unit groups each of which includes Mmultiplexing units 2 and second multiplexing unit groups each of whichincludes N multiplexing units 2. N and M are integers each greater than1, and M<N. The second multiplexing unit groups are in the middle offirst sub-region 921, and the first multiplexing unit groups are at twoends of the first sub-region 921 distal to the middle of the firstsub-region 921. And/or, in the second sub-region 922, the testing unitgroups include first testing unit groups and second testing unit groups.Each of the first testing unit groups includes K testing units 3, andeach of the second testing unit groups includes L testing units. L and Kare integers each greater than 1, and K<L. The second testing unitgroups are in the middle of the second sub-region 922, and the firsttesting unit groups are at two ends of the second sub-region 922 distalto the middle of the second sub-region 922.

In the middle of the first sub-region 921 (i.e., at an arc top of thesemicircular annulus), at least one second multiplexing unit group isprovided therein. Each of the at least one second multiplexing unitgroup includes N multiplexing units 2. At least one first multiplexingunit group is provided at the two ends of the first sub-region 921(i.e., the two ends or the opening of the semicircular annulus), andeach of the at least one first multiplexing unit group includes Mmultiplexing units 2, where M is less than N.

That is, the multiplexing unit groups (the second multiplexing unitgroups) are provided in the middle of the first sub-region 921, andincludes a larger number of multiplexing units 2. The multiplexing unitgroups (the first multiplexing unit groups) are provided at both ends ofthe first sub-region 921, and includes a smaller number of multiplexingunits 2. Thus, as a whole, a larger number of multiplexing units 2 and asmaller number of driving units 4 are provided in the middle of thefirst sub-region 921, and a smaller number of multiplexing units 2 and alarger number of driving units 4 are provided at both ends of the firstsub-region 921.

In some embodiments, N may be a value of 7, or 6, or 5; and in someembodiments, M may be a value of 1, or 2, or 3.

In some embodiments, there may be other multiplexing unit groups betweenthe first and second multiplexing unit groups, and a number ofmultiplexing units in these other multiplexing unit groups may be largerthan M and smaller than N.

At least one second testing unit group is provided in the middle of thesecond sub-region 922 (i.e., at an arc top of the semicircular annulus),and each of the at least one second testing unit group includes Ltesting units 3. At least one first testing unit group is provide at twoends (i.e., the two ends or the opening of the semicircular annulus) ofthe second sub-region 922, and each of the at least one first testingunit group includes K testing units 3, where K is less than L.

That is, the testing unit groups (the second testing unit groups) areprovided in the middle of the second sub-region 922, and includes alarger number of testing units 3. The testing unit groups (the firsttesting unit groups) are provided at both ends of the first sub-region921, and includes a smaller number of testing units 3. Thus, as a whole,a larger number of testing units 3 and a smaller number of driving units4 are provided in the middle of the second sub-section 922, and asmaller number of testing units 3 and a larger number of driving units 4are provided at the both ends of the second sub-section 922.

In some embodiments, L may be a value of 7, or 6, or 5; and in someembodiments, K may be a value of 1, or 2, or 3.

In some embodiments, other testing unit groups are provided between thefirst testing unit group and the second testing unit group, and a numberof testing units in the other testing unit groups may be larger than Kand smaller than L.

In some embodiments, in the first sub-region 921, in a direction fromthe two ends of the first sub-region 921 to the middle of the firstsub-region 921, the driving units 4 have gradually decreasingdistribution density, and the multiplexing units 2 have graduallyincreasing distribution density.

In the second sub-region 922, in a direction from the two ends of thesecond sub-region 922 to the middle of the second sub-region 922, thedriving units 4 have gradually decreasing distribution density, and thetesting units 3 have gradually increasing distribution density.

In each of the sub-regions of the circuit region 92, in the directionfrom the two ends of the sub-regions (i.e., positions adjacent to theother sub-region) to the middle of the sub-regions (i.e., a positionfurthest away the positions adjacent to the other sub-region), thedriving units 4 have gradually decreasing distribution density, and thetesting units 3 have gradually increasing distribution density.

The increasing distribution density of units A in a certain directiondoes not refer to that the number of the units A increases gradually atpositions where the units A are alternately arranged in the certaindirection, but only that the number of the units A gradually increasesfrom the overall distribution of the units A in a relatively largeregion in the certain direction.

The decreasing distribution density of units A in a certain directiondoes not refer to that the number of the units A decreases gradually atpositions where the units A are alternately arranged in the certaindirection, but only that the number of the units A gradually decreasesfrom the overall distribution of the units A in a relatively largeregion in the certain direction.

Exemplarily, referring to FIGS. 1 and 2, when the first sub-region 921and the second sub-region 922 include the above first and second arcregions respectively, the closer to the arc tops (the upper and lowersides of FIGS. 1 and 2) of the semicircular annulus of the above twosub-regions 921 and 922, less rows of sub-pixels 1 (i.e., a smallernumber of gate lines 12) and more columns of sub-pixels 1 (i.e., alarger number of data lines 11) correspond to a same arc length (or asame central angle) in the above two sub-regions 921 and 922. On thecontrary, the closer to the two ends or the opening (the middle along alongitudinal direction in the drawings) of the two semicircularannuluses, less columns of sub-pixels 1 (i.e., a smaller number of datalines 11) and more rows of sub-pixels 1 (i.e., a larger number of gatelines 12) correspond to a same arc length.

Therefore, referring to FIGS. 1 and 2, the “distribution density” of thedriving units 4 conforms to the following rule: in order to enable theunits to be coupled to corresponding row and column of sub-pixels 1nearby (or in a less distance), the closer to the arc top of thesemicircular annulus, the more the multiplexing units 2 or the testingunits 3 are, and the less the driving units 4 are; conversely, thecloser to the opening of the semicircular annulus, the less themultiplexing units 2 or the testing units 3 are, and the more thedriving units 4 are.

Of course, specific distribution positions and quantities, etc., of theunits in the circuit region 92 should be determined according tospecific distribution positions and quantities, etc., of the gate lines12, data lines 11, etc., in the display region 91, so as to make theunits close to their own connecting line as much as possible.

Exemplarily, referring to FIGS. 4 and 5, in a case where the firstsub-region 921 and the second sub-region 922 are the above first andsecond U-shaped regions respectively, the distribution density of themultiplexing units 2, the testing units 3, and the driving units 4 alsoconforms to the above rule.

That is, in the above two U-shaped regions, the closer to the tops (theupper and lower ends in FIGS. 4 and 5) of the U-shaped regions, lessrows of the sub-pixels 1 (i.e., a smaller number of gate lines 12) andmore columns of sub-pixels 1 (i.e., a larger number of data lines 11)correspond to a same side length; conversely, the closer to the two endsof the U-shaped regions (the middle along the longitudinal direction inFIGS. 4 and 5), less columns of sub-pixels 1 (i.e., a smaller number ofdata lines 11) and more rows of sub-pixels 1 (i.e., a larger number ofgate lines 12) correspond to a same side length.

Thus, referring to FIGS. 4 and 5, in order to enable the units to becoupled to corresponding row and column of sub-pixels 1 nearby, thecloser to the tops of the U-shaped regions, the more the multiplexingunits 2 or the testing units 3 are, and the less the driving units 4are; conversely, the closer to the openings of the U-shaped regions, theless the multiplexing units 2 or the testing units 3 are, and the morethe driving units 4 are, i.e., the “distribution density” of the drivingunits 4 conforms to the above rule.

A small number of units are shown in FIGS. 1, 2, 4 and 5 for clarity ofother structures, and the distribution density of the units may befurther shown in FIGS. 14 and 15 in detail.

In some embodiments, the circuit region 92 is divided into a first halfregion and a second half region opposite to each other on two sides ofthe display region 91 along the second direction 992.

The driving units 4 include a plurality of gate driving units 41.

The first half region is provided with a plurality of gate driving units41 configured to supply a gate driving signal to the plurality of gatelines 12.

Referring to FIGS. 1, 2, 4, and 5, the circuit region 92 may be furtherdivided into two “half regions” opposite to each other on the two sidesof the display region 91 along the second direction 992, and each of the“half regions” has a shape of a substantially semicircular annulus(e.g., a left semicircular annulus and a right semicircular annulus inFIGS. 1 and 2) or a U-shape (e.g., a left U-shape annulus and a rightU-shape annulus in FIGS. 4 and 5).

Since the gate lines 12 extend along the second direction 992, all thegate lines 12 correspond to the first half region (the left semicircularannulus in FIGS. 1 and 2, or the left U-shaped annulus in FIGS. 4 and5). Therefore, the driving units 4 in the first half region may includethe gate driving units 41 for providing a gate driving signal to theplurality of gate lines 12 (further, all the driving units 4 in thefirst half region 921 may be the gate driving units 41), so that thegate driving units 41 are coupled to corresponding gate lines 12 nearby.

Specifically, each of the gate driving units 41 may be a gate shiftregister (as a GOA (a gate driver on array)). A plurality of gate shiftregisters are cascaded, so that the plurality of gate shift registersmay respectively provide a driving signal to the plurality of gate lines12.

The gate shift register may have various specific forms. Exemplarily, acircuit structure and a driving timing of the gate shift register mayrefer to FIGS. 9 and 10. Hereinafter, signals of a low level may beequal to a low level signal VGL, and signals of a high level may beequal to a high level signal VGH.

In an input stage t1, a first gate clock signal CK is at a low level, asecond gate clock signal CB is at a high level, and an input signal STVis at a low level. Since the first gate clock signal CK is at the lowlevel, a second gate transistor K2 is turned on, and the input signalSTV is transmitted to a third gate node N3 via the second gatetransistor K2. Since the second gate transistor K2 has a threshold loss,the third gate node N3 is at a level of STV-Vth2, i.e., VGL-Vth2, whereVth2 represents a threshold voltage of the second gate transistor K2.Since a gate of a sixth gate transistor K6 receives the low level signalVGL, the sixth gate transistor K6 is turned on, and thus, the level ofVGL-Vth2 is transmitted to a first gate node N1 via the sixth gatetransistor K6. For example, a threshold level of the sixth gatetransistor K6 is denoted as Vth6. Similarly, since the sixth gatetransistor K6 has a threshold loss, the first gate node N1 is at a levelof VGL-VthN1, where VthN1 is the smaller one of the Vth2 and the Vth 6.The level at the first gate node N1 may be used to control an eighthgate transistor K8 to be turned on. The second gate clock signal CB isoutput as a gate output signal GOUT via the eighth gate transistor K8,i.e., in the input stage t1, the gate output signal GOUT is the secondgate clock signal CB with a high level, i.e., the gate output signalGOUT is equal to VGH.

In the input phase t1, since the first gate clock signal CK is at thelow level, a first gate transistor K1 is turned on, the low level signalVGL is transmitted to a second gate node N2 via the first gatetransistor K1. Since the level at the third gate node N3 is VGL-Vth2, aseventh gate transistor K7 is turned on, and the low level of the firstgate clock signal CK is transmitted to the second gate node N2 via theseventh gate transistor K7. For example, a threshold voltage of theseventh gate transistor K7 is denoted as Vth7, and a threshold voltageof the first gate transistor K1 is denoted as Vth1. When Vth1<Vth7+Vth2,the level at the second gate node N2 is VGL−Vth7−Vth 2; and whenVth1>Vth7+Vth2, the level at the second gate node N2 is VGL−Vth1. Inthis case, both the third gate transistor K3 and the fourth gatetransistor K4 are turned on. Since the second gate clock signal CB is atthe high level, the fifth gate transistor K5 is turned off.

In an output stage t2, the first gate clock signal CK is at a highlevel, the second gate clock signal CB is at a low level, and the inputsignal SKT is at a high level. An eighth gate transistor K8 is turnedon, and the second gate clock signal CB is output as the gate outputsignal GOUT via the eighth gate transistor K8. In the input phase t1, alevel at one terminal of a second gate capacitor C2 coupled to the firstgate node N1 is VGL−VthN1, and a level at the other terminal of thesecond gate capacitor C2 is a high level. In the output stage t2, thelevel at the terminal of the second gate capacitor C2 coupled to anoutput terminal GOUT is changed to VGL. Due to bootstrap of the secondgate capacitor C2, the level at the terminal of the second gatecapacitor C2 coupled to the first gate node N1 is changed to2VGL−VthN1−VGH, that is, the level at the first gate node N1 becomes2VGL−VthN1−VGH. In this case, the sixth gate transistor K6 is turnedoff, the eighth gate transistor K8 may be turned on better, and the gateoutput signal GOUT is the low level signal VGL.

In the output stage t2, the first gate clock signal CK is at the highlevel, so that both the second gate transistor K2 and the first gatetransistor K1 are turned off. The level at the third gate node N3 isstill maintained at VGL−VthN1, the seventh gate transistor K7 is turnedon, and the first gate clock signal CK of the high level is transmittedto the second gate node N2 via the seventh gate transistor K7, that is,the level at the second gate node N2 is VGH. Thus, both the third gatetransistor K3 and the fourth gate transistor K4 are turned off. Sincethe second gate clock signal CB is at the low level, the fifth gatetransistor K5 is turned on.

In a buffering stage t3, the first gate clock signal CK and the secondgate clock signal CB are both at a high level, and the input signal SKTis at a high level. The eighth gate transistor K8 is turned on, and thesecond gate clock signal CB is output as the gate output signal GOUT viathe eighth gate transistor K8. In this case, the gate output signal GOUTis the second gate clock signal CB with the high level, i.e., VGH. Thelevel at the first gate node N1 is changed to VGL−VthN1 due to thebootstrap of the second gate capacitor C2.

In the buffering period t3, the first gate clock signal CK is at thehigh level, so that both the second gate transistor K2 and the firstgate transistor K1 are turned off The level at the first gate node N1 ischanged to VGL−VthN1. In this case, the sixth gate transistor K6 isturned on, the level at the third gate node N3 is also VGL−VthN1, theseventh gate transistor K7 is turned on, the first gate clock signal CKof the high level is transmitted to the second gate node N2 via theseventh gate transistor K7, that is, the level at the second gate nodeN2 is VGH. Thus, both the third gate transistor K3 and the fourth gatetransistor K4 are turned off. Since the second gate clock signal CB isat the high level, the fifth gate transistor K5 is turned off.

In a first sub-stage t41 of a stabilization stage t4, the first gateclock signal CK is at a low level, the second gate clock signal CB is ata high level, and the input signal SKT is at a high level. Since thefirst gate clock signal CK is at the low level, the second gatetransistor K2 is turned on, and the input signal SKT is transmitted tothe third gate node N3 via the second gate transistor K2. Since a highlevel is transmitted via the second gate transistor K2 without thresholdloss, a level at the third gate node N3 is VGH, and the seventh gatetransistor K7 is turned off. Since the sixth gate transistor K6 isturned on, the level at the first gate node N1 is the same as that atthe third gate node N3, that is, the level at the first gate node N1 isVGH, and the eighth gate transistor K8 is turned off. Since the firstgate clock signal CK is at the low level, the first gate transistor K1is turned on, the level at the second gate node N2 is VGL−Vth1, both thethird gate transistor K3 and the fourth gate transistor K4 are turnedon, and the high level signal VGH is output as the gate output signalGOUT via the third gate transistor K3, that is, the gate output signalis the high level signal VGH.

In a second sub-stage t42 of the stabilization stage t4, the first gateclock signal is at a high level, the second gate clock signal is at alow level, and the input signal SKT is at a high level. The levels atboth the first gate node N1 and the third gate node N3 are VGH, and boththe eighth gate transistor K8 and the seventh gate transistor K7 areturned off. Since the first gate clock signal CK is at the high level,both the second gate transistor K2 and the first gate transistor K1 areturned off. Due to voltage holding of the first gate capacitor C1, thelevel at the second gate node N2 is still VGL−Vth1, both the third gatetransistor K3 and the fourth gate transistor K4 are turned on, and thehigh level signal VGH is output as the gate output signal GOUT via thethird gate transistor K3, that is, the gate output signal is the highlevel signal VGH.

In the second sub-stage t42, since the second gate clock signal CB is atthe low level, the fifth gate transistor K5 is turned on, and thus thehigh level signal VGH is transmitted to the third gate node N3 and thefirst gate node N1 via the fourth gate transistor K4 and the fifth gatetransistor K5, so that the levels at both the first gate node N1 and thethird gate node N3 are maintained at a high level.

In a third sub-stage t43 of the stabilization stage t4, both the firstgate clock signal CK and the second gate clock signal CB are at a highlevel, and the input signal SKT is at a high level. The levels at boththe first gate node N1 and the third gate node N3 are VGH, and theeighth gate transistor K8 and the seventh gate transistor K7 are turnedoff. Since the first gate clock signal CK is at the high level, both thesecond gate transistor K2 and the first gate transistor K1 are turnedoff, the level at the second gate node N2 is still VGL−Vth1, and boththe third gate transistor K3 and the fourth gate transistor K4 areturned on. The high level signal VGH is output as the gate output signalGOUT via the third gate transistor K3, i.e., the gate output signal isthe high level signal VGH.

In some embodiments, the display region 91 is further provided with aplurality of control electrode lines 13 extending in the seconddirection 992, each of the control electrode lines 13 is coupled tomultiple sub-pixels 1.

The driving units 4 are control electrode driving units 42.

The second half region is provided with a plurality of control electrodedriving units 42 configured to supply a control electrode driving signalto the plurality of control electrode lines 13.

Referring to FIGS. 1, 2, 4 and 5, the display region 91 may be furtherprovided with control electrode lines 13 extending along the seconddirection 992, and each of the control electrode lines 13 may also becoupled to one or two rows of sub-pixels 1, and in particular a controlelectrode line 13 may be coupled to the control electrode line terminalEM of the above 7T1C pixel circuit.

Since the control electrode lines 13 also extend along the seconddirection 992, all the control electrode lines 13 correspond to thedriving units 4 in the second half-region (i.e., the right semicircularannulus in FIGS. 1 and 2, or the right U-shaped annulus in FIGS. 4 and5), and therefore, the driving units 4 in the second half-region may beprovided with the control electrode driving units 42 for providing acontrol electrode driving signal to the plurality of control electrodelines 13 (further, each of the driving units 4 in the second half-region922 may be the control electrode driving unit 42), so that the controlelectrode driving units 42 are coupled to corresponding control lines 13nearby.

Thus, referring to FIGS. 1, 2, 4, and 5, in the circuit region 92 of thedisplay substrate according to the embodiment of the present disclosure,the testing units 3 and the gate driving units 41 are mixed in arrangedin an upper left region, the testing units 3 and the control electrodedriving units 42 are mixed in arranged in an upper right region, themultiplexing units 2 and the gate driving units 41 are mixed in arrangedin a lower left region, and the multiplexing units 2 and the controlelectrode driving units 42 are mixed in arranged in a lower rightregion.

Referring to FIGS. 1 and 2, since an annulus has different radialdirections at different positions of the annulus, the units arranged inthe annulus may also be “rotated” with different arrangement positions,and generally, output terminals of the units are always ensured to facea center of a circle as edges of the annulus.

In addition, referring to FIGS. 4 and 5, the units arrangedcorresponding to the above “arc boundary” may also be “rotated” withdifferent arrangement positions, and generally, output terminals of theunits is always ensured to face a center of a circle a part of which isthe arc boundary.

Of course, it will be appreciated that, the units and the sub-pixels 1in FIGS. 1, 2, 4 and 5 is merely schematically shown as a rectangle.However, in practice, each of the units and the sub-pixels 1 isconstituted of a plurality of elements, and a region occupied by each ofthe units and the sub-pixels 1 is not necessarily of a rectangle.

Of course, it will be appreciated that, for an actual display substrate,each of the units occupies only a small region of an annulus region, sothat in some subsequent drawings, many structures of each of the unitsat partial region may be approximately simplified as straight lines.

Of course, it should be appreciated that, in many drawings of theembodiments of the present disclosure, due to the limitation of an areaof the display substrate, a shape, a size, a size ratio, a number, anumber ratio, positions, and the like of various structures of thesub-pixel 1, such as lines (e.g., signal lines), joints, units, regions,and the like, are only illustrative and not restrictive. For example,the actual number of testing signal lines 63, driving signal lines 64,and the like should be more than those shown in FIGS. 1, 2, 4, and 5.

Of course, the above specific form of the driving units 4 is not alimitation to the embodiment of the present disclosure.

For example, all the driving units 4 in both the two half regions may bethe gate driving units 41 and respectively provide the gate drivingsignal for different gate lines 12, or provide the gate driving signalfor each of the gate lines 12 from both sides of each of the gate lines12 (i.e., in double-side driving mode).

Specifically, each of the control electrode driving units 42 may be acontrol electrode shift register (EM GOA). A plurality of controlelectrode shift registers are cascaded, so that the plurality of controlelectrode shift registers may respectively provide a driving signal tothe plurality of control electrode lines 13.

The control electrode shift register may be of various specific forms.Exemplarily, a circuit structure and a driving timing of the controlelectrode shift register may refer to FIGS. 11 and 12. Hereinafter, alow level of the signal may be equal to a low level signal VGL, and ahigh level of the signal may be equal to a high level signal VGH.

In a first stage P1, a first control electrode clock signal CK′ is at alow level, so that a first control electrode transistor M1 and a thirdcontrol electrode transistor M3 are turned on. A high level start signalESTV is transmitted to a first control electrode node N1′ via theturned-on first control electrode transistor M1, so that a level at thefirst control electrode node N1′ is changed to a high level, and thus asecond control electrode transistor M2, an eighth control electrodetransistor M8 and a tenth control electrode transistor M10 are turnedoff. In addition, the low level signal VGL is transmitted to the secondcontrol electrode node N2′ via the turned-on third control electrodetransistor M3, so that a level at the second control electrode node N2′is changed to a low level, and thus a fifth control electrode transistorM5 and a sixth control electrode transistor M6 are turned on. Since asecond control electrode clock signal CB′ is at a high level, a seventhcontrol electrode transistor M7 is turned off. In addition, a level at afourth control electrode node N4′ may be maintained at a high level dueto charge storage of a third control electrode capacitance C3′, so thata ninth control electrode transistor M9 is turned off. In the firststage P1, since both the ninth control electrode transistor M9 and thetenth control electrode transistor M10 are turned off, a controlelectrode output signal EMOUT is maintained at a previous low level.

In a second stage P2, the second control electrode clock signal CB′ isat a low level, and thus a fourth control electrode transistor M4 andthe seventh control electrode transistor M7 are turned on. Since thefirst control electrode clock signal CK′ is at a high level, the firstcontrol electrode transistor M1 and the third control electrodetransistor M3 are turned off. The second control electrode node N2′ maycontinue to be maintained at a low level of a previous stage due tocharge storage of a first control electrode capacitor C1′, so that thefifth control electrode transistor M5 and the sixth control electrodetransistor M6 are turned on. The high level signal VGH is transmitted tothe first control electrode node N1′ via the turned-on fifth and fourthcontrol electrode transistors M5 and M4, so that the level at the firstcontrol electrode node N1′ is maintained at a high level of a previousstage, and thus the second control electrode transistor M2, the eighthcontrol electrode transistor M8, and the tenth control electrodetransistor M10 are turned off. In addition, the second control electrodeclock signal CB′ of the low level is transmitted to the fourth controlelectrode node N4′ via the turned-on sixth and seventh control electrodetransistor M6 and M7, so that a level at the fourth control electrodenode N4′ is changed to a low level, and thus the ninth control electrodetransistor M9 is turned on. The high level signal VGH is output via theturned-on ninth control electrode transistor M9, and thus the controlelectrode output signal EMOUT is a high level.

In a third stage P3, since the first control electrode clock signal CK′is at a low level, the first control electrode transistor M1 and thethird control electrode transistor M3 are turned on. Since the secondcontrol electrode clock signal CB′ is at a high level, the fourthcontrol electrode transistor M4 and the seventh control electrodetransistor M7 are turned off. Due to charge storage of a third controlelectrode capacitor C3′, a level at the fourth control electrode nodeN4′ may be maintained at a low level in a previous stage, so that theninth control electrode transistor M9 is maintained to be turned on. Theturned-on ninth control electrode transistor M9 outputs the high levelsignal VGH, so that the control electrode output signal EMOUT is stillat the high level.

In a fourth stage P4, since the first control electrode clock signal CK′is at a high level, the first control electrode transistor M1 and thethird control electrode transistor M3 are turned off. Since the secondcontrol electrode clock signal CB′ is at a low level, the fourth controlelectrode transistor M4 and the seventh control electrode transistor M7are turned on. Due to charge storage of a second control electrodecapacitor C2′, the level at the first control electrode node N1′ ismaintained at a high level of a previous stage, so that the secondcontrol electrode transistor M2, the eighth control electrode transistorM8, and the tenth control electrode transistor M10 are turned off. Dueto the charge storage of the first control electrode capacitor C1′, thesecond control electrode node N2 continues to be maintained at the lowlevel in a previous stage, so that the fifth control electrodetransistor M5 and the sixth control electrode transistor M6 are turnedon. In addition, the second control electrode clock signal CB′ of thelow level is transmitted to the fourth control electrode node N4′ viathe turned-on sixth control electrode transistor M6 and the turned-onseventh control electrode transistor M7, so that the level at the fourthcontrol electrode node N4′ is changed to a low level, and thus the ninthcontrol electrode transistor M9 is turned on. The high level signal VGHis output via the turned-on ninth control electrode transistor M9, andthus the control electrode output signal EMOUT is still maintained atthe high level.

In a fifth stage P5, since the first control electrode clock signal CK′is at a low level, the first control electrode transistor M1 and thethird control electrode transistor M3 are turned on. Since the secondcontrol electrode clock signal CB′ is at a high level, the fourthcontrol electrode transistor M4 and the seventh control electrodetransistor M7 are turned off. The start signal ESTV of a low level istransmitted to the first control electrode node N1′ via the turned-onfirst control electrode transistor M1, so that the level at the firstcontrol electrode node N1′ is changed to a low level, and thus thesecond control electrode transistor M2, the eighth control electrodetransistor M8, and the tenth control electrode transistor M10 are turnedon. The first control electrode clock signal CK′ of a low level istransmitted to the second control electrode node N2′ via the turned-onsecond control electrode transistor M2, so that the level at the secondcontrol electrode node N2′ may be further lowered. Therefore, the secondcontrol electrode node N2′ continues to be maintained at the low levelof a previous stage, so that the fifth control electrode transistor M5and the sixth control electrode transistor M6 are turned on. Inaddition, the high level signal VGH is transmitted to the fourth controlelectrode node N4′ via the turned-on eighth control electrode transistorM8, so that the level at the fourth control electrode node N4′ ischanged to a high level, and thus the ninth control electrode transistorM9 is turned off. Since the low level signal VGL is output via theturned on tenth control electrode transistor M10, the control electrodeoutput signal EMOUT is changed to a low level.

In some embodiments, the multiplexing signal lines 62 include aplurality of multiplexing control lines 621 and a plurality ofmultiplexing data lines 622.

At least one of the multiplexing units 2 includes a plurality ofmultiplexing transistors 21. A gate of each of the plurality ofmultiplexing transistor 21 is coupled to one multiplexing control line621, a first electrode is coupled to one data line 11, and a secondelectrode is coupled to one multiplexing data line 622.

The second electrodes of all multiplexing transistors 21 in a samemultiplexing unit 2 are coupled to a same multiplexing data line 621,and the second electrodes of the multiplexing transistors 21 indifferent multiplexing units 2 are coupled to different multiplexingdata lines 622.

Referring to FIGS. 1, 2, 4, 5 and 6, the multiplexing signal lines 62include multiplexing control lines 621 and multiplexing data lines 622,and each of the multiplexing units 2 includes a plurality ofmultiplexing transistors 21 (six transistors 21 shown in FIG. 6 as anexample). A gate of each of the multiplexing transistors 21 is coupledto the multiplexing control line 621, a first electrode of each of themultiplexing transistors 21 is coupled to the data line 11, and a secondelectrode of each of the multiplexing transistors 21 is coupled to themultiplexing data line 622. And, a same multiplexing unit 2 is coupledto a same multiplexing data line 622, and different multiplexing units 2are coupled to different multiplexing data lines 622.

Thus, referring to FIG. 6, when displaying, ON signals (signals capableof turning on transistors) may be in turn input to one of the pluralityof multiplexing control lines 621, and OFF signals (signals capable ofturning off transistors) are input to the other of the plurality ofmultiplexing control lines 621, such that one multiplexing data line 622is alternately communicating with different data lines 11 via theplurality of multiplexing transistors 21 in one multiplexing unit 2,thereby providing required data signals to multiple data lines 11 viaone multiplexing data line 622 respectively. That is, control of theplurality of data lines 11 by one signal source (e.g., via the joints 6)(i.e., “one driving many”, e.g., one driving six) is achieved, therebymaking the number of signal sources providing signals to the data lines11 much smaller than the number of data lines 11, so as to simplify aproduct structure, e.g., to reduce the number of required driving chips.

In view of simplifying structures, the number of the multiplexingcontrol lines 621 may be equal to the number of the multiplexingtransistors 21 in each of the multiplexing units 2 (e.g., themultiplexing control lines 621 includes six multiplexing control lines,and the multiplexing transistors 21 in each of the multiplexing units 2includes six multiplexing transistors 21), that is, the multiplexingtransistors 21 in each of the multiplexing units 2 may be coupled todifferent multiplexing control lines 621 respectively, and each of themultiplexing control lines 621 is coupled to a corresponding onemultiplexing transistor 21 in each of the multiplexing units 2.

Since the multiplexing control line 621 needs to be coupled to multiplemultiplexing units 2, the multiplexing control line 621 may have aportion extending along a circumferential direction of the fan-outregion 93. Different parts of the portion are coupled to differentmultiplexing units 2 respectively. Each of the multiplexing data lines622 is coupled to only one multiplexing unit 2, and thus each of themultiplexing data lines 622 may be directly coupled to correspondingmultiplexing unit 2 across the fan-out region 93.

Obviously, based on the above structure, a small number of multiplexingdata lines 621 is located at positions in the fan-out region 93 along acircumferential direction of the fan-out region 93 farther from aconnection sub-region 923, and thus the fan-out region 93 may have asmaller size.

In some embodiments, the testing signal lines 63 include testing controllines 631 and testing data lines 632.

At least one testing unit 3 includes a plurality of testing transistors31. A gate of each of the testing transistors 31 is coupled to onetesting control line 631, a first electrode of each of the testingtransistors 31 is coupled to one data line 11, and a second electrode ofeach of the testing transistors 31 is coupled to one testing data line632.

Each of the testing data lines 632 is coupled to the plurality oftesting units 3. Referring to FIGS. 1, 2, 4, 5, 7 and 8, the testingsignal lines 63 include testing control lines 631 and testing data lines632. Correspondingly, each of the testing units 3 may include aplurality of testing transistors 31. A gate of each of the testingtransistors 31 is coupled to the testing control line 631, a firstelectrode of each of the testing transistors 31 is coupled to the dataline 11, and a second electrode of each of the testing transistors 31 iscoupled to the testing data line 632. Thus, by applying ON signals tothe testing control lines 631, signals in the testing data lines 632 maybe input correspondingly to the plurality of data lines 11 via thetesting transistors 31 in different testing units, so as to achievedetection of the display device.

Since each of the testing data lines 632 is coupled to the plurality oftesting units 3, the number of the testing data lines 632 is muchsmaller than the number of the testing units 3. Therefore, although thetesting units 3 are located away from the joint region 94, since controlof the testing units 3 may be achieved by only a few testing signallines 63 extending to the testing units 3, the a few testing signallines 63 do not occupy a large layout area.

The correspondence relationship between the testing data lines 632, thetesting control lines 631, and the testing units 3 may be various.

For example, referring to FIG. 7, the number of the testing data lines632 may be equal to the number of the testing transistors 31 in each ofthe testing units 3 (e.g., the number of the testing data lines 632 isthree, and the number of the testing transistors 31 in each of thetesting units 3 is three), and the number of the testing control lines631 is only one. That is, each of the testing data lines 632 is coupledto a second electrode of one testing transistor 31 in each of thetesting units 3, first electrodes of different testing transistors 31are coupled to different data lines 11, and gates of all the testingtransistors 31 of all the testing units 3 are coupled to the one testingcontrol line 631.

In this case, referring to FIG. 7, the color of the sub-pixels 1 coupledto each of the data lines 11 may be the same (in the drawing, Rrepresents a red sub-pixel 1, G represents a green sub-pixel 1, and Brepresents a blue sub-pixel 1), and the color of the sub-pixels 1coupled to the data line 11 corresponding to each of the testing dataline 632 is the same. Therefore, a same testing signal is consecutivelyapplied to the testing data lines 632, so that the sub-pixels 1 of asame color may display a same brightness (for example, an overalldisplay of a white picture or other monochrome pictures), to facilitateto position poor sub-pixels 1.

For another example, the colors of the sub-pixels 1 coupled to each ofthe data lines 11 may be different. Referring to FIG. 8, each fourcolumns of sub-pixels 1 include two columns of green sub-pixels 1, andthe other two columns of sub-pixels in each of which the red and bluesub-pixels 1 are alternately arranged. In the two columns of sub-pixels1 other than the two columns of green sub-pixels 1, any two adjacentsub-pixels 1 in any same row are blue and red, respectively.

Further, referring to FIG. 8, three testing data lines 632, threetesting control lines 631 and five testing transistors 31 in each of thetesting units 3 are shown for controlling four data lines 11(corresponding to the above four columns of sub-pixels 1). Firstelectrodes of a first testing transistor 311 and a third testingtransistor 313 of each of the testing units 3 are coupled to one columnof sub-pixels 1 in which the red and blue sub-pixels 1 are alternatelyarranged. First electrodes of a second testing transistor 312 and afourth testing transistor 314 of each of the testing units 3 are coupledto the other column of sub-pixels 1 in which the red and blue sub-pixels1 are alternately arranged. Second electrodes of the first testingtransistor 311 and the second testing transistor 312 are coupled to afirst testing data line 6321. Second electrodes of the third testingtransistor 313 and the fourth testing transistor 314 are coupled to asecond testing data line 6322. Gates of the first testing transistor 311and the fourth testing transistor 314 are coupled to a first testingcontrol line 6311. Gates of the second testing transistor 312 and thethird testing transistor 313 are coupled to a second testing controlline 6312. A gate of the fifth testing transistor 315 is coupled to athird testing control line 6313, a first electrode of the fifth testingtransistor 315 is coupled to two columns of green sub-pixels 1, and asecond electrode of the fifth testing transistor 315 is coupled to athird testing data line 6323.

As can be seen from the above arrangement, by providing the ON signalsin turn to the first testing control line 6311 and the second testingcontrol line 6312, the blue and red sub-pixels 1 may be controlled bythe first testing data line 6321 and the second testing data line 6322respectively, while all the green sub-pixels 1 may be controlled by thethird testing control line 6313 and the third testing data line 6323, sothat the sub-pixels 1 of the same color may display the same brightness.

In some embodiments, the testing signal lines 63 are on a side of thecircuit region 92 distal to the display region 91, and the drivingsignal lines 64 are on a side of the circuit region 92 distal to thedisplay region 91.

Referring to FIGS. 1, 2, 4, 5 and 13, in order to facilitate to becoupled to corresponding units, the testing signal lines 63 and thedriving signal lines 64 may be arranged along a side of (outside) thecircuit region 92 distal to the display region 91. Of course, since thefan-out region 93 is also outside the circuit region 92, the testingsignal lines 63 and the driving signal lines 64 are also partially inthe fan-out region 93.

The specific number of the testing signal lines 63 and the drivingsignal lines 64 may be determined according to different forms of theircorresponding units.

For example, when the testing unit 3 is of a form as shown in FIG. 7,the testing signal lines 63 may include three testing data lines 632 andone testing control line 631, i.e., a total of four testing signal lines63 are arranged around the outside of the circuit region 92.

For another example, when the gate driving unit 41 is of a form as shownin FIG. 9, four corresponding driving signal lines 64 may be neededrespectively for transmitting the first gate clock signal CK, the secondgate clock signal CB, the high level signal VGH, and the low levelsignal VGL.

For another example, when the control electrode driving unit 42 is of aform as shown in FIG. 11, four corresponding driving signal lines 64 maybe needed respectively for transmitting the first control electrodeclock signal CK′, the second control electrode clock signal CB′, thehigh level signal VGH, and the low level signal VGL.

Since the first gate clock signal CK, the second gate clock signal CB,the first control electrode clock signal CK′, and the second controlelectrode clock signal CB′ are different from each other, they may becoupled to corresponding four different driving signal lines 64. Sincethe high level signal VGH and the low level signal VGL for the gatedriving units 41 and the control electrode driving units 42 may berespectively the same, the high level signal VGH for all the units maybe transmitted via one driving signal line 64 (e.g., a high level line641), and the low level signal VGL for all the units may be transmittedvia one driving signal line 64 (e.g., a low level line 642). Of course,the high level line 641 and the low level line 642 should be distributedat positions outside the first half region and the second half region ofthe circuit region 92.

Exemplarily, referring to FIGS. 1, 2, 4, 5, and 13, the above testingsignal lines 63 may be on a side of (outside) the driving signal lines64 distal to the display region 91.

In some embodiments, ends of the first sub-region 921 closest to thesecond sub-region 922 are closer to the display region 91 than ends ofthe second sub-region 922 closest to the first sub-region 921.

Referring to FIGS. 1, 2 and 13, since an inner side of the secondsub-region 922 is further provided with the capacitor region 95, and aninner side of the first sub-region 921 is provided with the displayregion 91, the first sub-region 921 may be “further inside (furthercloser to the display region 91)” than the second sub-region 922.Therefore, the first sub-region 921 is also “further inside” than thesecond sub-region 922 at adjacent ends of the two sub-regions. Forexample, a radius (one halt of an inner or external diameter) of thefirst semicircular annulus may be smaller than that of the secondsemicircular annulus.

Of course, when the first sub-region 921 and the second sub-region 922do not include the above “arc region” but include regions of any othershape, the term “radius” may not be used to describe the first andsecond sub-regions, but their ends may still satisfy the abovepositional relationship, i.e., the first sub-region 921 may still be“smaller” than the second sub-region 922.

In some embodiments, the circuit region 92 further includes: connectionsub-regions 923 connecting the ends of the first sub-region 921 closestto the second sub-region 922 and the ends of the second sub-region 922closest to the first sub-region 921 respectively.

Referring to FIG. 13, the ends of the first sub-region 921 are “furtherinside” than the ends of the second sub-region 922, so that the ends ofthe first sub-region 921 are not “aligned” with the ends of the secondsub-section 922, and the connection sub-regions 923 obliquely arrangedmay be needed to connect the first sub-region 921 and the secondsub-region 922.

It should be understood that the connection sub-regions 923 also belongto the circuit region 92, and the driving units 4 may also be providedin the connection sub-regions 923. However, since the connectionsub-regions 923 are not the first sub-region 921 or the secondsub-region 922, there is no multiplexing unit 2 and no testing powersupply. However, for the sake of structural regularity, structures inthe connection sub-region 923 should be as simple as possible, forexample, only including necessary lines (such as, lines for cascadingdifferent driving units 4).

Meanwhile, correspondingly, for the sake of structural regularity, thetesting signal lines 63 and the driving signal lines 64 outside thecircuit region 92 may also be bent at corresponding connectionsub-region 923, so as to ensure substantially unchanged distancesbetween the test signal line 63 and the circuit region 92, and betweenthe driving signal line 64 and the circuit region 92.

In some embodiments, the display substrate in the embodiment of thepresent disclosure further includes: at least one polysilicon resistor71. Each of the at least one polysilicon resistor 71 is between andcoupled to two signal lines. The polysilicon resistor 71 is on a side ofthe ends of the first sub-region 921 closest to the second sub-region922, distal to the display region 91, or on a side of the connectionsub-region 923 distal to the display region 91.

The polysilicon resistor 71 is also called a “poly resistor”, which is aresistor made of polysilicon (p-Si) material having a relatively largeresistance. The polysilicon resistor 71 achieves connection betweendifferent signal lines, so that when there is no signal in one signalline, the signal in the other signal line may reach the one signal lineto some extent after delay, thereby avoiding signal fluctuation in thesignal lines due to floating. Meanwhile, when there is a signal in boththe two signal lines, since the polysilicon resistor 71 has a largeresistance, the two signal lines are not short-circuited, and thesignals in the two signal lines are not affected by each other.

In order to achieve a resistance as large as possible in a layout areaas small as possible, the polysilicon resistor 71 may be of a structureformed by bending the polysilicon material with a shape of a line in asmall region.

As mentioned above, the ends of the first sub-region 921 is “furtherinside” than the ends of the second sub-region 922, so that the ends ofthe first sub-region 921 and outer sides of the connection sub-region923 relatively “reserve” a certain space where polysilicon resistors 71may be located, referring to FIGS. 1, 2 and 13. For example, the ends ofthe first sub-region 921 at two sides (left and right sides in FIGS. 1and 2) of the display substrate along the second direction 992 and theouter sides of the connection sub-regions 923 may be provided with thepolysilicon resistors 71.

In some embodiments, the test signal lines 63 are on a side of thecircuit region 92 distal to the display region 91.

The driving signal lines 64 are on a side of the circuit region 92distal to the display region 91.

The polysilicon resistors 71 are on a side of the testing signal lines63 and the driving signal lines 64 distal to the display region 91.

Referring to FIGS. 1, 2 and 13, when the testing signal line 63 and thedriving signal lines 64 are also outside the circuit region 92, thepolysilicon resistors 71 may be provided outside the signal lines toprevent the polysilicon resistors 71 from affecting the connectionbetween the signal lines and corresponding units in the circuit region92.

In some embodiments, the display substrate in the embodiments of thepresent disclosure further includes: at least one electrostaticdischarge unit 72. Each of the at least one electrostatic discharge unit72 is coupled to one signal line, and is configured to discharge staticelectricity in the signal line to which it is coupled. The electrostaticdischarge unit 72 is on a side of the ends of the first sub-region 921closest to the second sub-region 922, distal to the display region 91,or is on a side of the connection sub-region 923 distal to the displayregion 91.

In order to prevent the signal lines from being damaged by dischargebreakdown due to accumulation of static electricity in the signal lines,electrostatic discharge units 72 (ESD) may be further provided todischarge the static electricity accumulated in the signal lines,thereby protecting the signal lines.

As mentioned above, the ends of the first sub-region 921 are “furtherinside” than the ends of the second sub-region 922, so that the ends ofthe first sub-region 921 and the outer side of the connection sub-region923 relatively “reserve” a certain space where the electrostaticdischarge units 72 may be located, referring to FIGS. 1, 2 and 13. Forexample, the ends of the first sub-region 921 at two sides (left andright sides in FIGS. 1 and 2) of the display substrate along the seconddirection 992 and the outer sides of the connection sub-region 923 maybe provided with the electrostatic discharge units 72.

The region occupied by the polysilicon resistors 71 and theelectrostatic discharge units 72 should not exceed the region defined bythe position difference between the ends of the first sub-region 921 andthe ends of the second sub-region 922, for example, a size of each ofthe polysilicon resistors 71 and the electrostatic discharge units 72may be in a range from 100 μm to 150 μm.

Of course, even when the size of the first sub-region 921 is not smallerthan the size of the second sub-region 922 (e.g., the sub-regionincludes a U-shaped region), referring to FIG. 4, the polysiliconresistors 71 and the electrostatic discharge units 72 may be arrangedoutside the boundary between the first sub-region 921 and the secondsub-region 922.

It should be understood that the polysilicon resistors 71 (e.g., firstpolysilicon resistors 711 and second polysilicon resistors 712) shown inthe circuit diagrams (e.g., FIGS. 7 and 16) in the embodiments of thepresent disclosure only represent electrical connection structures ofthe polysilicon resistors 71, and do not represent physical positionrelationship between the polysilicon resistors 71 and other units.

In some embodiments, the testing signal lines 63 are on a side of thecircuit region 92 distal to the display region 91.

The driving signal lines 64 are on a side of the circuit region 92distal to the display region 91.

The electrostatic discharge units 72 are on a side of the testing signallines 63 and the driving signal lines 64 distal to the display region91.

Referring to FIGS. 1, 2, 4, 5 and 13, when the testing signal lines 63and the driving signal lines 64 are outside the circuit region 92, theelectrostatic discharge units 72 may also be outside the signal lines toprevent the electrostatic discharge units 72 from affecting theconnection between the signal lines and corresponding units in thecircuit region 92.

In some embodiments, the multiplexing signal lines 62 include aplurality of multiplexing control lines 621 and a plurality ofmultiplexing data lines 621. The signal line to which each of theelectrostatic discharge units 72 is coupled is the testing signal line63 or the multiplexing control line 621.

Referring to FIG. 13, there may be a plurality of electrostaticdischarge units 72, which are coupled to and protects the above testingsignal lines 63 (e.g., four testing signal lines 63) and themultiplexing control lines 621 (e.g., six multiplexing control lines621), respectively.

In some embodiments, the driving signal lines 64 include a high levelline 641 and a low level line 642. The high level line 641 is configuredto be coupled to a high level signal source, and the low level line 642is configured to be coupled to a low level signal source.

Each of the electrostatic discharge units 72 includes a first dischargetransistor 721 and a second discharge transistor 722. A gate and a firstelectrode of the first discharge transistor 721 are coupled to the highlevel line 641, and a second electrode of the first discharge transistor721 is coupled to a signal line (the testing signal line 63 or themultiplexing control line 621) corresponding to the electrostaticdischarge unit 72. A gate and a first electrode of the second dischargetransistor 722 are coupled to a signal line corresponding to theelectrostatic discharge unit 72, and a second electrode of the seconddischarge transistor 722 is coupled to the low level line 642.

Referring to FIGS. 13 and 16, as a form of the embodiment of the presentdisclosure, the electrostatic discharge unit 72 may include twodischarge transistors. One electrode and a gate of each of the twodischarge transistors are coupled to each other, thereby forming anequivalent diode connection. A signal line to be protected is betweenand respectively coupled to two terminals of two “diodes” formed by thetwo discharge transistors. The other two terminals of the two “diodes”are coupled to the above high level line 641 (for transmitting the highlevel signal VGH) and the low level line 642 (for transmitting the lowlevel signal VGL), respectively. Thus, when an instantaneous highvoltage (e.g., 100V) occurs in the signal line due to accumulation ofpositive charges, the “diode” in the first discharge transistor 721 isturned on, thereby discharging the positive charges in the signal line.When an instantaneous low voltage (e.g., −100V) occurs in the signalline due to accumulation of negative charges, the “diode” in the seconddischarge transistor 722 is turned on, thereby discharging the negativecharges in the signal line.

In some embodiments, the polysilicon resistors 71 include firstpolysilicon resistors 711. Two signal lines coupled to each of the firstpolysilicon resistors 711 are the high level line 641 and the testcontrol line 631, respectively.

Referring to FIGS. 7 and 13, at least some of the polysilicon resistors71 (the first polysilicon resistors 711) may be between and coupled tothe high level line 641 (for transmitting the high level signal VGH) andthe testing control line 631 (for transmitting the control signal fromthe testing unit 3). When a test (e.g., an ET test) is performed, an ONsignal or an OFF signal as required is provided to the testing controlline 631, and the first polysilicon resistor 711 is used to prevent thetesting control line 631 from being influenced by the high level signalVGH. When a normal display is performed and no test is performed, an OFFsignal of a fixed value may be applied to the testing control line 631,and the first polysilicon resistor 711 ensures the stability of thelevel of the OFF signal.

In some embodiments, the polysilicon resistors 71 include secondpolysilicon resistors 712. Two signal lines coupled to each of thesecond polysilicon resistors 712 are the high level line 641 and thesignal line corresponding to the electrostatic discharge unit 72respectively.

Referring to FIGS. 13 and 16, at least some of the polysilicon resistors71 (the second polysilicon resistors 712) may be between and coupled tothe high level line 641 (for transmitting the high level signal VGH) andthe signal line (the testing signal line 63 or the multiplexing controlline 621) corresponding to the electrostatic discharge unit 72 to avoidan excessively high level.

Of course, it should be understood that, since different electrostaticdischarge units 72 correspond to different signal lines, differentelectrostatic discharge units 72 should also be coupled to differentsecond polysilicon resistors 712, i.e., the number of second polysiliconresistors 712 may be the same as the number of electrostatic dischargeunits 72. However, in FIG. 13, only some of the second polysiliconresistors 712 are shown for clarity of connection.

In some embodiments, at least some of different data lines 11 arecoupled to different number of sub-pixels 1.

Except for the data line 11 coupled to the largest number of sub-pixels1, each of the remaining data lines 11 is coupled to one compensationcapacitor unit 5.

Referring to FIGS. 1 and 2, in some cases, different data lines 11 arecoupled to different numbers of sub-pixels 1. For example, when thedisplay region 91 has a shape of a substantial circle and each of thedata lines 11 is coupled to a column of sub-pixels 1, since differentnumbers of sub-pixels 1 are provided in different columns, differentdata lines 11 are coupled to different numbers of sub-pixels 1.

Obviously, each of the sub-pixels 1, as a pixel capacitor, has a certaincapacitance, and the pixel capacitor is regarded as a “load” of the dataline 11 coupled thereto. Therefore, the data lines 11 are coupled todifferent numbers of sub-pixels 1, resulting in different loads ofdifferent data lines 11. Thus, when a same signal is applied to the datalines 11, the signals actually obtained by the sub-pixels 1 coupled todifferent data lines 11 are different, which affects the displayquality.

Therefore, except the data line 11 coupled to the largest number ofsub-pixels 1 (i.e., the data line 11 with the largest load), theremaining data lines 11 each may be coupled to the compensationcapacitor unit 5. The compensation capacitor unit 5 is used for “adding(or compensating)” a certain load to the data line 11, such that all thedata lines 11 each have a total load (total capacitance) as close aspossible, and a uniform display may be achieved.

In some embodiments, each of compensation capacitance units 5 includesone or more compensation capacitors 51.

Except for the data line 11 coupled to the largest number of sub-pixels1, a number n of the compensation capacitors 51 in the compensationcapacitor unit 5 coupled to the remaining data lines 11 satisfies:

N=Nmax−N;

where Nmax is the number of sub-pixels 1 coupled to the data line 11coupled to the largest number of sub-pixels 1, and N is the number ofsub-pixels 1 coupled to the data line 11 coupled to the compensationcapacitor unit 5.

Referring to FIG. 17, each of the compensation capacitor units 5 mayinclude a plurality of compensation capacitors 51. A number of thecompensation capacitors 51 is equal to the difference between the number(N) of sub-pixels 1 coupled to the data line 11 corresponding to thecompensation capacitor unit 5 and the number Nmax of sub-pixels 1coupled to the data line 11 coupled to the largest number of sub-pixels1. In this way, as long as the capacitance of a single compensationcapacitor 51 is substantially equal to the capacitance of a singlesub-pixel 1, a total capacitance (total load) coupled to each of all thedata lines 11 after being compensated may be substantially the same.

Generally, firstly, a plurality of actual sub-pixels 1 may be preparedand an actual capacitance of a single sub-pixel 1 is detected. Then, anactual size of the compensation capacitor 51 is determined based on theactual capacitance. Specifically, in order to reduce error, the totalcapacitance of a plurality of sub-pixels 1 (e.g., ten) is generallydetected and divided by the number of sub-pixels 1 (e.g., ten) to obtainthe capacitance of a single sub-pixel 1 (generally in a range from about20˜30 fF).

In some embodiments, the data line 11 is coupled to the first electrodesof all the compensation capacitors 51 in the compensation capacitor unit5 coupled thereto.

The second electrodes of the compensation capacitors 51 each are coupledto a same constant level signal line.

Referring to FIG. 17, specifically, the data line 11 may be coupled toone electrode of each of the compensation capacitors 51 in thecorresponding compensation capacitor unit 5, and the other electrode ofeach of all the compensation capacitors 51 may be coupled to a constantlevel signal line to obtain a same constant level. Exemplary, the otherelectrode of all the compensation capacitors 51 may be coupled to ananode signal line 19 for supplying power to an anode signal terminal VDDof the pixel circuit.

In some embodiments, the multiple sub-pixels 1 connected by each of thedata lines 11 are arranged in a column along the first direction 991.

The compensation capacitor unit 5 coupled to each of the data lines 11is provided between the column of sub-pixels 1 coupled to the data line11 and the second sub-region 922 along the first direction 991.

Referring to FIG. 17, in a case where the sub-pixels 1 are arranged inmultiple columns and each of the data lines 11 is coupled to one columnof sub-pixels 1, a smaller number of sub-pixels 1 are in a “shorter”column, a larger number of compensation capacitors 51 are in thecorresponding compensation capacitor unit 5, and a larger area isoccupied by the compensation capacitor unit 5. Therefore, for sake offully utilizing space, the compensation capacitance unit 5 may beprovided between the sub-pixels 1 in a corresponding column and thesecond sub-region 922.

Of course, connection relationship, specific forms, position, etc., ofthe compensation capacitor units 5 described above are not intended tolimit the scope of the embodiments of the present disclosure.

In a second aspect, a display device is provided in the embodiment ofthe present disclosure. The display device includes any one of the abovedisplay substrates.

The above display substrate may be combined with other components (e.g.,a pair-box cover plate, a flexible wiring board, a driving chip, a powersupply module, etc.) to form a display device having a display function.

In some embodiments, the display device is a wearable display device.

In particular, the above display device is particularly suitable as awearable display device wearable on a human body, for example, thedisplay device may be a smart watch or the like worn on a wrist of aperson.

Of course, the wearable display device may further include a watch bandor the like for wearing on the human body.

Of course, the above display device is not limited to a wearable displaydevice, and may also be any product or component having a displayfunction, such as electronic paper, a mobile phone, a tablet computer, atelevision, a display, a notebook computer, a digital photo frame, and anavigator.

The present disclosure has disclosed example embodiments, and althoughspecific terms are employed, they are used and should be interpreted ina generic and descriptive sense only and not for purposes of limitation.In some instances, features, characteristics and/or elements describedin connection with a particular embodiment may be used alone or incombination with features, characteristics and/or elements described inconnection with other embodiments, unless expressly stated otherwise, aswould be apparent to one skilled in the art. It will, therefore, beunderstood by those skilled in the art that various changes in form anddetails may be made therein without departing from the scope of thedisclosure as set forth in the appended claims.

1. A display substrate, comprising a display region and a peripheralregion, the peripheral region comprising a capacitor region, a circuitregion, a fan-out region and a joint region, wherein the display regionis provided with: a plurality of sub-pixels; a plurality of data linesextending along a first direction, each of the plurality of data linesbeing coupled to multiple sub-pixels; and a plurality of gate linesextending in a second direction intersecting the first direction, eachof the plurality of gate lines being coupled to multiple sub-pixels, thecircuit region is provided with a first sub-region and a secondsub-region which are opposite to each other at two sides of the displayregion along the first direction, respectively, the first sub-region isprovided with a plurality of multiplexing unit groups configured toprovide data signals to the plurality of data lines, and each of themultiplexing unit groups comprises at least one multiplexing unit; thesecond sub-region is provided with a plurality of testing unit groupsconfigured to provide testing signals to the plurality of data lines,and each of the plurality of testing unit groups comprises at least onetesting unit; the circuit region is further provided with a plurality ofdriving unit groups, each of the driving unit groups comprises at leastone driving unit; the driving unit groups and the multiplexing unitgroups are alternately arranged in the first sub-region along anextending direction of the first sub-region, and the driving unit groupsand the testing unit groups are alternately arranged in the secondsub-region along an extending direction of the second sub-region; thecapacitor region is between the second sub-region and the displayregion, and is provided with a plurality of compensation capacitorunits, and each of the plurality of compensation capacitor units iscoupled to one of the plurality of data lines, the joint region is on aside of the first sub-region distal to the display region and comprisesa plurality of joints, at least some of the plurality of joints arecoupled to signal lines, the signal lines comprise multiplexing signallines coupled to multiplexing units, testing signal lines coupled totesting units and driving signal lines coupled to driving units; and thefan-out region is between the joint region and the first sub-region, andis provided with the multiplexing signal lines.
 2. The display substrateof claim 1, wherein the first sub-region comprises a first arc region,the second sub-region comprises a second arc region, and an edge of thefirst arc region proximal to the display region is closer to a center ofthe display region than an edge of the second arc region proximal to thedisplay region.
 3. The display substrate of claim 2, wherein the firstarc region has a same circle center as the second arc region, and aradius of the edge of the first arc region proximal to the displayregion is smaller than a radius of the edge of the second arc regionproximal to the display region by 210 μm˜420 μm.
 4. The displaysubstrate of claim 3, wherein in the first sub-region, the multiplexingunit groups comprise first multiplexing unit groups and secondmultiplexing unit groups, each of the first multiplexing unit groupscomprises M multiplexing units, each of the second multiplexing unitgroups comprises N multiplexing units, N and M are integers each greaterthan 1, and M<N, the second multiplexing unit groups are in the middleof the first sub-region, the first multiplexing unit groups are at twoends of the first sub-region distal to the middle of the firstsub-region; and/or in the second sub-region, the testing unit groupscomprise first testing unit groups and second testing unit groups, eachof the first testing unit groups comprises K testing units, each of thesecond testing unit groups comprises L testing units, L and K areintegers each greater than 1, and K<L, the second testing unit groupsare in the middle of the second sub-region, and the first testing unitgroups are at two ends of the second sub-region distal to the middle ofthe second sub-region.
 5. The display substrate of claim 4, wherein thecircuit region is divided into a first half region and a second halfregion which are opposite to each other at two sides of the displayregion along the second direction; the driving units comprise aplurality of gate driving units; and the first half region is providedwith multiple gate driving units configured to provide a gate drivingsignal to the plurality of gate lines.
 6. The display substrate of claim5, wherein the display region is further provided with a plurality ofcontrol electrode lines extending along the second direction, and eachof the plurality of control electrode line is coupled to multiplesub-pixels; the driving units further comprises a plurality of controlelectrode driving units; and the second half region is provided with aplurality of control electrode driving units configured to provide acontrol electrode driving signal to the plurality of control electrodelines.
 7. The display substrate of claim 6, wherein the multiplexingsignal lines comprise a plurality of multiplexing control lines and aplurality of multiplexing data lines; at least one of the multiplexingunits includes a plurality of multiplexing transistors; a gate of eachof the plurality of multiplexing transistors is coupled to one of themultiplexing control lines, a first electrode of each of themultiplexing transistors is coupled to one of the data lines, and asecond electrode of each of the multiplexing transistors is coupled toone of the multiplexing data lines; and second electrodes of allmultiplexing transistors in a same multiplexing unit are coupled to asame multiplexing data line, and second electrodes of the multiplexingtransistors in different multiplexing units are coupled to differentmultiplexing data lines.
 8. The display substrate of claim 7, whereinthe testing signal lines comprise testing control lines and testing datalines; at least one of the testing units comprises a plurality oftesting transistors; a gate of each of the plurality of testingtransistors is coupled to one of the testing control lines, a firstelectrode of each of the plurality of testing transistors is coupled toone of the data lines, and a second electrode of each of the pluralityof testing transistors is coupled to one of the testing data line; andeach of the testing data lines is coupled to multiple testing units. 9.The display substrate of claim 8, wherein the testing signal lines areon a side of the circuit region distal to the display region; and thedriving signal lines are on a side of the circuit region distal to thedisplay region.
 10. The display substrate of claim 9, wherein ends ofthe first sub-region closest to the second sub-region are closer to thedisplay region than ends of the second sub-region closest to the firstsub-region.
 11. The display substrate of claim 10, wherein the circuitregion further comprises: connection sub-regions which are between andcoupled to the ends of the first sub-region closest to the secondsub-region and the ends of the second sub-region closest to the firstsub-region.
 12. The display substrate of claim 11, further comprising atleast one polysilicon resistor, wherein each of the at least onepolysilicon resistor is between and coupled to two of the signal lines,the polysilicon resistor is on a side of the end of the first sub-regionclosest to the second sub-region, distal to the display region, or thepolysilicon resistor is on a side of the connection sub-region distal tothe display region.
 13. The display substrate of claim 12, wherein thetesting signal lines are on a side of the circuit region distal to thedisplay region; the driving signal lines are on a side of the circuitregion distal to the display region; and the polysilicon resistor is ona side of the testing signal lines and the driving signal lines distalto the display region.
 14. The display substrate of claim 11, furthercomprising at least one electrostatic discharge unit, wherein each ofthe at least one electrostatic discharge unit is coupled to one of thesignal lines and configured to release static charges in the signal lineto which it is coupled; the electrostatic discharge unit is on a side ofthe end of the first sub-region closest to the second sub-region, distalto the display region, or the electrostatic discharge unit is on a sideof the connection sub-region distal to the display region.
 15. Thedisplay substrate of claim 14, wherein the testing signal lines are on aside of the circuit region distal to the display region; the drivingsignal lines are on a side of the circuit region distal to the displayregion; and the electrostatic discharge units are on a side of thetesting signal lines and the driving signal lines distal to the displayregion.
 16. The display substrate of claim 14, wherein the multiplexingsignal lines comprise a plurality of multiplexing control lines and aplurality of multiplexing data lines; and the signal lines coupled toeach of electrostatic discharge units are the testing signal lines orthe multiplexing control lines.
 17. The display substrate of claim 14,wherein the driving signal lines comprise a high level line and a lowlevel line, the high level line is coupled to a high level signalsource, and the low level line is coupled to a low level signal source;and each of the electrostatic discharge units comprises a firstdischarge transistor and a second discharge transistor; a gate and afirst electrode of the first discharge transistor are coupled to thehigh level line, and a second electrode of the first dischargetransistor is coupled to the signal line corresponding to theelectrostatic discharge unit; and a gate and a first electrode of thesecond discharge transistor are coupled to the signal line correspondingto the electrostatic discharge unit, and a second electrode of thesecond discharge transistor is coupled to the low level line.
 18. Thedisplay substrate of claim 15, wherein at least some of different datalines are coupled to different numbers of sub-pixels; and except for thedata line coupled to a largest number of sub-pixels, each of theremaining data lines is coupled to one of the compensation capacitorunits.
 19. The display substrate of claim 18, wherein each of thecompensation capacitor units comprises one or more compensationcapacitors; except for the data line coupled to the largest number ofsub-pixels, the number n of the compensation capacitors in thecompensation capacitor unit coupled to each of the remaining data lines,satisfies:N=Nmax−N; wherein Nmax is the number of the sub-pixels coupled to thedata line coupled to the largest number of the sub-pixels, and N is thenumber of the sub-pixels coupled to the data line coupled to thecompensation capacitor unit.
 20. The display substrate of claim 19,wherein the data line is coupled to first electrodes of all thecompensation capacitors in the compensation capacitor unit coupled tothe data line; and second electrodes of all the compensation capacitorsin the compensation capacitor unit are coupled to a same constant levelsignal line; or wherein multiple sub-pixels coupled to each of the datalines are arranged in a column along the first direction; and thecompensation capacitor unit coupled to each of the data lines is betweena column of sub-pixels coupled to the data line and the secondsub-region along the first direction. 21-24. (canceled)